flush_dcache_all() is expected to write back and invalidate every level of the data cache, but on Andes it only flushes L1. Flush L2 through the cache uclass as well.
Until the L2 cache device is probed, andes_l2_flush_all() returns without touching the hardware, as andes_l2_enable() and andes_l2_disable() already do. flush_dcache_range() and invalidate_dcache_range() call flush_dcache_all(), so they now flush the whole L2 cache too. Flushing by physical address is left out to keep this change small. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Randolph Lin <[email protected]> --- arch/riscv/cpu/andes/cache.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c index bb57498d75a..30d766da8f9 100644 --- a/arch/riscv/cpu/andes/cache.c +++ b/arch/riscv/cpu/andes/cache.c @@ -44,6 +44,10 @@ static void cache_ops(int (*ops)(struct udevice *dev)) void flush_dcache_all(void) { csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); + +#ifdef CONFIG_ANDES_L2_CACHE + cache_ops(cache_flush_all); +#endif } void flush_dcache_range(unsigned long start, unsigned long end) -- 2.34.1
