On Andes, flush_dcache_all() only flushes L1, and flush_dcache_range() and invalidate_dcache_range() call it. Without the I/O coherence port (IOCP), DMA masters do not snoop the CPU caches, so dirty lines left in L2 make them read stale data.
This series adds a flush_all operation to the cache uclass, implements it in the Andes L2 cache driver and calls it from flush_dcache_all(). In U-Boot proper, enable_caches() runs before driver model is set up after relocation and cannot find the L2 cache device, so patch 4 runs it again once driver model is ready. U-Boot proper in S-mode then drives L2 itself, as the Linux ax45mp_cache driver does. Side effects: each range operation flushes the whole L2 cache, "dcache off" and "dcache on" turn L2 off and on in S-mode, and L2 is now enabled in M-mode U-Boot proper. checkpatch warns about the #ifdef in patch 3, which matches the rest of the file, and does not know the Assisted-by tag from Linux's Documentation/process/coding-assistants.rst. Randolph Lin (4): dm: cache: Add flush_all operation cache: andes-l2: implement flush_all riscv: andes: flush the L2 cache in flush_dcache_all() riscv: andes: probe the L2 cache device in U-Boot proper arch/riscv/cpu/andes/cache.c | 19 +++++++++++++++++++ drivers/cache/cache-andes-l2.c | 16 ++++++++++++++-- drivers/cache/cache-uclass.c | 10 ++++++++++ include/cache.h | 16 ++++++++++++++++ 4 files changed, 59 insertions(+), 2 deletions(-) -- 2.34.1
