Hi Jonas,
On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote:
> clk: rockchip: rk3576: Use correct PLL rate for UART divisor
>
> Calculate the UART divisor from the CPLL rate instead of the GPLL rate
> when CPLL is selected as parent clock.
>
> Fixes: 3919310b37ec ("clk: rockchip: Add rk3576 clk support")
> Signed-off-by: Jonas Karlman <[email protected]>
>
> drivers/clk/rockchip/clk_rk3576.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> diff --git a/drivers/clk/rockchip/clk_rk3576.c
> b/drivers/clk/rockchip/clk_rk3576.c
> @@ -1843,7 +1843,7 @@ static ulong rk3576_uart_set_rate(struct
> rk3576_clk_priv *priv,
> - div = DIV_ROUND_UP(priv->gpll_hz, rate);
> + div = DIV_ROUND_UP(priv->cpll_hz, rate);
BTW rk3576_uart_get_rate() a little higher up has a similar bug. For
UART1 it uses the shift as the mask:
src = (con & CLK_UART1_SRC_SEL_SHIFT) >> CLK_UART1_SRC_SEL_SHIFT;
so src is always 0 (GPLL) and SCLK_UART1 reports the wrong rate
whenever another parent is selected. It should use
CLK_UART1_SRC_SEL_MASK instead. That could go in a separate patch in
this series, or in a follow-up.
Reviewed-by: Simon Glass <[email protected]>
