On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote: > clk: rockchip: rk3588: Use correct PLL rate for SCLK_UARTx divider > > Calculate the divider from the CPLL rate instead of the GPLL rate when > CPLL is selected as the SCLK_UARTx parent. > > Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support") > Signed-off-by: Jonas Karlman <[email protected]> > > drivers/clk/rockchip/clk_rk3588.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass <[email protected]>
