The KICKPI K1 is a RK3568B2-based single board computer with eMMC, microSD card slot, dual Gigabit Ethernet (Maxio MAE0621A PHYs with on-board crystals) and a 1500000 baud serial console on UART2.
Add a minimal device tree enabling eMMC, SD-card, UART2, USB OTG and both GMACs, together with a defconfig to boot from eMMC or SD-card. Signed-off-by: Yuming Chen <[email protected]> --- arch/arm/dts/rk3568-kickpi-k1-u-boot.dtsi | 3 + arch/arm/dts/rk3568-kickpi-k1.dts | 226 ++++++++++++++++++++++ board/rockchip/evb_rk3568/MAINTAINERS | 6 + configs/kickpi-k1-rk3568_defconfig | 62 ++++++ doc/board/rockchip/rockchip.rst | 1 + 5 files changed, 298 insertions(+) create mode 100644 arch/arm/dts/rk3568-kickpi-k1-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-kickpi-k1.dts create mode 100644 configs/kickpi-k1-rk3568_defconfig diff --git a/arch/arm/dts/rk3568-kickpi-k1-u-boot.dtsi b/arch/arm/dts/rk3568-kickpi-k1-u-boot.dtsi new file mode 100644 index 00000000000..6e8307e3bdf --- /dev/null +++ b/arch/arm/dts/rk3568-kickpi-k1-u-boot.dtsi @@ -0,0 +1,3 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk356x-u-boot.dtsi" diff --git a/arch/arm/dts/rk3568-kickpi-k1.dts b/arch/arm/dts/rk3568-kickpi-k1.dts new file mode 100644 index 00000000000..798a275e6cf --- /dev/null +++ b/arch/arm/dts/rk3568-kickpi-k1.dts @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * KickPi K1 (RK3568) minimal U-Boot device tree. + * Boot essentials only: eMMC, SD-card, UART2 console and USB OTG, + * modeled after rk3568-generic.dts. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3568.dtsi" + +/ { + model = "KICKPI K1"; + compatible = "rockchip,rk3568-kickpi-k1a", "rockchip,rk3568"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + /* + * IO-domain rails as routed on the K1A board (vendor kernel + * rk3568-kickpi-evb.dtsi). Rails are RK809 outputs already up at + * reset; U-Boot only needs their voltage to program the PMU GRF + * VSEL bits. GMAC0 pads live in VCCIO4 and GMAC1 pads in VCCIO6, + * both 1.8V -- leaving these unset selects the 3.3V class and the + * RGMII pads never work. + */ + vcc3v3_pmu: regulator-vcc3v3-pmu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_acodec: regulator-vccio-acodec { + compatible = "regulator-fixed"; + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vccio_sd: regulator-vccio-sd { + compatible = "regulator-fixed"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + no-mmc; + no-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +/* Rail map identical to vendor kernel rk3568-kickpi-evb.dtsi */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&usb_host0_xhci { + dr_mode = "peripheral"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +/* Dual GbE, Maxio MAE0621A PHYs with on-board crystals, RGMII with SoC-side + * delays (clock/pinctrl config per SDK eth dtsi, identical to mainline BPI-R2 + * Pro). The MAE0621A needs its vendor driver (drivers/net/phy/maxio.c) before + * its RGMII RX clock runs. + */ + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + /* RGMII delays are provided by the SoC via the tx_delay/rx_delay GRF + * registers below, not by the PHY or PCB traces + */ + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset timing per vendor SDK dtsi (generic PHY reset delays) */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x21>; + rx_delay = <0x3c>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + /* RGMII delays are provided by the SoC via the tx_delay/rx_delay GRF + * registers below, not by the PHY or PCB traces + */ + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset timing per vendor SDK dtsi (generic PHY reset delays) */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x2f>; + rx_delay = <0x39>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +/* + * RK809 PMIC on i2c0 (same bus as vendor kernel dts). Binding it here lets + * U-Boot enable boot-on rails: without vdd_npu up before the kernel starts, + * powering the NPU power domain never gets a PMU ack and the vendor kernel + * panics (pm_domains.c panic_on_set_idle). + */ +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + + regulators { + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_npu"; + }; + }; + }; +}; diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 3a655a817f4..375b649ad2e 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -40,6 +40,12 @@ M: Coia Prant <[email protected]> S: Maintained F: configs/graperain-g3568-v2-rk3568_defconfig +KICKPI-K1 +M: Yuming Chen <[email protected]> +S: Maintained +F: configs/kickpi-k1-rk3568_defconfig +F: arch/arm/dts/rk3568-kickpi-k1* + LUBANCAT-2 M: Andy Yan <[email protected]> S: Maintained diff --git a/configs/kickpi-k1-rk3568_defconfig b/configs/kickpi-k1-rk3568_defconfig new file mode 100644 index 00000000000..2e4012609d5 --- /dev/null +++ b/configs/kickpi-k1-rk3568_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rk3568-kickpi-k1" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-kickpi-k1.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_MAXIO=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index e22c2d6c575..4e0d3a78f88 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -137,6 +137,7 @@ List of mainline supported Rockchip boards: - Generic RK3566/RK3568 (generic-rk3568) - Graperain G3568 v2 (graperain-g3568-v2-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) + - KICKPI K1 (kickpi-k1-rk3568) - LinkEase EasePi R1 (easepi-r1-rk3568) - Lunzn FastRhino R66S (fastrhino-r66s-rk3568) - QNAP TS-433 (qnap-ts433-rk3568) -- 2.55.0
