On 2026-10-11T22:28:36, Jonas Karlman <[email protected]> wrote: > clk: rockchip: rk3568: Use correct PLL rate for CLK_MAC0_2TOP > > Use the PPLL rate instead of HPLL rate when the PPLL is parent of the > CLK_MAC0_2TOP clock. > > Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver") > Signed-off-by: Jonas Karlman <[email protected]> > Reviewed-by: Quentin Schulz <[email protected]> > > drivers/clk/rockchip/clk_rk3568.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass <[email protected]>
