Mark the UFS host controller and its UFS configuration clock controllers for SPL, so that SPL can load the firmware FIT from UFS when the UFS devicetree overlay enables the controller.
Signed-off-by: David Lechner <[email protected]> --- arch/arm/dts/mt8371-genio-common-u-boot.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/mt8371-genio-common-u-boot.dtsi b/arch/arm/dts/mt8371-genio-common-u-boot.dtsi index 70c538a690e..7f614323c93 100644 --- a/arch/arm/dts/mt8371-genio-common-u-boot.dtsi +++ b/arch/arm/dts/mt8371-genio-common-u-boot.dtsi @@ -32,7 +32,10 @@ }; &gic { - /* Retain the eMMC interrupt parent even though SPL uses polling. */ + /* + * Retain the storage controllers' interrupt parent even though SPL + * uses polling. + */ bootph-pre-ram; }; @@ -64,6 +67,18 @@ bootph-pre-ram; }; +&ufshci { + bootph-pre-ram; +}; + +&ufscfg_ao_reg_clk { + bootph-pre-ram; +}; + +&ufscfg_pdn_reg_clk { + bootph-pre-ram; +}; + &mmc0_default_pins { bootph-pre-ram; -- 2.53.0
