Do not issue the UFS SiP SMCs when U-Boot itself runs at EL3. There is no secure monitor to handle them then, e.g. in SPL before BL31 has been loaded, and an SMC would trap into U-Boot's own exception vectors.
The SiP calls only notify the secure world about the reference clock and drive the device reset pin. The firmware stage that ran before SPL has already brought up the UFS device, so the host can still be initialized without them. Signed-off-by: David Lechner <[email protected]> --- drivers/ufs/ufs-mediatek-sip.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/ufs/ufs-mediatek-sip.h b/drivers/ufs/ufs-mediatek-sip.h index 6a61f7bac69..cb27da1458c 100644 --- a/drivers/ufs/ufs-mediatek-sip.h +++ b/drivers/ufs/ufs-mediatek-sip.h @@ -9,6 +9,7 @@ #ifndef _UFS_MEDIATEK_SIP_H #define _UFS_MEDIATEK_SIP_H +#include <asm/system.h> #include <linux/arm-smccc.h> /* @@ -37,6 +38,10 @@ struct ufs_mtk_smc_arg { static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s) { + /* No secure monitor to call yet, e.g. in SPL before BL31. */ + if (current_el() == 3) + return; + arm_smccc_smc(MTK_SIP_UFS_CONTROL, s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); -- 2.53.0
