(for my case) defines in section 9.5 the configuration space for the VF.
Most entries are RO for the VF, and I found no writable register bit
behaving in a similar manner than the referred "adding register", but I
might overlook something.
Ryan could you still verify this or are more experienced to find such a
reg for me in the spec?
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A a single PCI read or write appears twice on the PCIe bus. This
happens when using the SR-IOV feature with some PCI devices
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