------- Comment From [email protected] 2024-10-07 20:50 EDT------- (In reply to comment #3) > Last 30 lines of memcheck5.log below (whole file has 65 lines). > pmempool_feature/TEST5 memcheck5.log ==1397154== Illegal opcode at address > 0x4B59240 > pmempool_feature/TEST5 memcheck5.log ==1397154== at 0x4B59240: ppc_flush > (init.c:53)
Looking at the source at init.c:53, that is: asm volatile(__DCBF(0, %0, 6) : :"r"(uptr) : "memory"); The dcbf instruction is a RA|0 instruction, meaning the base address is its RA operand and its value is either the contents of RA for RA = r1-r31 or the value zero if RA = 0 (regardless of the contents of r0). My guess is that the valgrind error you are seeing is because the base register is r0 and that doesn't make sense. The reason you could get r0 as a base register here is because for RA|0 operands, you should never use the "r" register constraint, which tells the compiler you want any register between r0 - r31. You need to use the "b" constraint here which tells the compiler to give you a register between r1 - r31. ...so this is a user source error. The fix is: --- a/src/libpmem2/ppc64/init.c +++ b/src/libpmem2/ppc64/init.c @@ -50,7 +50,7 @@ ppc_flush(const void *addr, size_t size) * According to the POWER ISA 3.1, dcbstps (aka. dcbf (L=6)) * behaves as dcbf (L=0) on previous processors. */ - asm volatile(__DCBF(0, %0, 6) : :"r"(uptr) : "memory"); + asm volatile(__DCBF(0, %0, 6) : :"b"(uptr) : "memory"); uptr += CACHELINE_SIZE; } -- You received this bug notification because you are a member of Ubuntu Bugs, which is subscribed to Ubuntu. https://bugs.launchpad.net/bugs/2061913 Title: PMDK FTBFS on ppc64el obj_basic_integration/TEST5 crashed To manage notifications about this bug go to: https://bugs.launchpad.net/pmdk/+bug/2061913/+subscriptions -- ubuntu-bugs mailing list [email protected] https://lists.ubuntu.com/mailman/listinfo/ubuntu-bugs
