------- Comment From [email protected] 2024-10-07 22:21 EDT------- (In reply to comment #9) > Actually, looking closer, this isn't what valgrind is complaining about. > I'm a looking deeper.
The pmdk code change where this was introduced was: - /* issue a dcbst instruction for the cache line */ - asm volatile( - "dcbst 0,%0" - : :"r"(uptr) : "memory"); + /* + * Flush the data cache block. + * According to the POWER ISA 3.1, dcbstps (aka. dcbf (L=6)) + * behaves as dcbf (L=0) on previous processors. + */ + asm volatile(__DCBF(0, %0, 6) : :"r"(uptr) : "memory"); I think the problem here is that valgrind is being too smart and recognizing that the "dcbf r0,RB,6" version of the instruction is a Power10 version of dcbf where the extra L operand was added. When I execute a simple binary with "dcbf r0,RB,6" on a Power10 system (assuming RB points to some real memory), it executes fine and valgrind has no problem with it. If I take the same binary and execute it on a Power9 system, then it again executes fine, but valgrind flags the dcbf instruction as illegal. If it is true that L=6 should act like L=0 on older than Power10 cpus, then valgrind shouldn't flag the instruction as illegal when run on those older cpus. I'll verify L=6 is ok on Power9 and earlier with our hardware team and will talk with my valgrind developer about a fix if that is the case. If it is not true, the pmdk has a source bug. I'll report back what I find out. -- You received this bug notification because you are a member of Ubuntu Bugs, which is subscribed to Ubuntu. https://bugs.launchpad.net/bugs/2061913 Title: PMDK FTBFS on ppc64el obj_basic_integration/TEST5 crashed To manage notifications about this bug go to: https://bugs.launchpad.net/pmdk/+bug/2061913/+subscriptions -- ubuntu-bugs mailing list [email protected] https://lists.ubuntu.com/mailman/listinfo/ubuntu-bugs
