To have a very localized fix just to the issue we see I tried O2 with

diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index a68809eef3..5317d8be57 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -189,6 +189,13 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint32_t 
ctr_idx)
  *  env->priv and env->virt_enabled contain old priv and old virt and
  *  new priv and new virt values are passed in as arguments.
  */
+#if defined(__powerpc64__) || defined(__ppc64__)
+  #define NO_GCSE_ATTR __attribute__((optimize("no-gcse")))
+#else
+  #define NO_GCSE_ATTR
+#endif
+
+NO_GCSE_ATTR
 static void riscv_pmu_icount_update_priv(CPURISCVState *env,
                                          target_ulong newpriv, bool new_virt)
 {


If that works we have our mitigation and I have enough to report upstream gcc 
as well as FYI to qemu for their consideration. I'll also copy some of the 
binaries here to ease debugging.

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https://bugs.launchpad.net/bugs/2120835

Title:
  EDK2 tests for riscv emulation fail against qemu 10.1 on ppc64el

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