Michael Schnell wrote:
> Michael Schnell wrote:
> > disables the global interrupt for the next three
> > instructions.
>
> True for the NIOS, that does not use "Flags" - but register compares -
> for conditional jumps, with an architecture that uses flags, I suppose
> you need a lock for four instructions.
That sounds right.
Three instructions is also enough for atomic-add, atomic-sub,
atomic-and etc. in addition to compare-exchange.
Although compare-exchange is universal, sometimes it takes more time
busy spinning compared with an atomic arithmetic or logical operation,
when under high contention with multiple CPUs.
Four instructions is enough for a versatile logic sequence:
LOAD [addr], reg
AND #xxx, reg
XOR #yyy, reg
STORE reg, [addr]
-- Jamie
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