>Date: Wed, 23 Oct 2002 10:03:09 -0500
>From: "Phil A. Lefebvre" <[EMAIL PROTECTED]>
>Subject: Re: Quartz Extreme & IDE Hard Drive question
>
>On 10/22/02 at 11:01 PM -0700, Charles Baker wrote:
>>I have Quartz Extreme enabled on my 9600/300...
>>
>>A 33MHz/32-bit PCI bus can sustain 132 MB/sec throughput.
>
>That's the theoretical limit, but most Old World machines,
>especcially those saddled with PCI 2.0 slots (all those prior to the
>Mach 5 and Beige G3)
Are you sure the Mach 5 has an improved PCI bus? I've installed the
Kansas ROMs in the x500 machines and haven't noticed much difference
in PCI behaviour. The Kansas/Mach 5 machines use the same Bandit
chips and such, so the only component likely to be making a
difference is the updated ROM.
> will have a hard time taking advantage of that
>bandwidth. On the 8500 List people report having a hard time getting
>over 40 MB/s of real world sustained throughput with RAIDs that
>should be capable of faster. I know on my old 8500, AV stuttering is
>a problem with my SCSI, FW or IDE cards. I wouldn't be surprised if a
>9600 as a more robust PCI bus.
To elaborate on Phil's point a bit. From Apple's "Designing PCI
Cards and Drivers for Power Macintosh Computers", available in PDF
from Apple's site:
> Assuming that neither the initiator nor the target inserts wait
>states during each
> data phase, the maximum theoretical bandwidth over a 32-bit bus is 132
> Mbytes/second. This also assumes continuous bursting with a 32-bit
>data object
> transferred on each PCI clock cycle. (Apple's implementation incorporates a
> 32-bit data bus.)
> Because the IB chip competes for system memory along with other system
> devices, continuous PCI bursting is not possible. Therefore, the
>achievable PCI
> bandwidth on Power Macintosh computers is less than the PCI theoretical
> maximum. Also, the bandwidth is dependent on the PCI target's hardware
> design and the architecture of the driver software.
Table 1-5 PowerPC processor to PCI maximum bandwidth summary
PCI PowerPC
Transaction Bytes per bandwidth,
setup
Bus master description transaction MB/s
Processor Write To PCI 4 20
Integer Store
Processor Write To PCI 8 40
Floating Point Store
Processor Write To PCI 32 85 PCI Copyback
Processor Read from PCI 4 11 Integer Load
Processor Read from PCI 8 20
Floating point Load
Processor Read from PCI 32 40 PCI WriteThru
I hope that lines up properly.
The curious thing about the above table is that the reports I've seen
from folks have shown that they can often manage the 85 MB/s rate or
thereabouts for PCI reads, but only 40 MB/s or so for writes, which
is the reverse of what the table indicates.
Still, 40 MB/s in one direction and 80 - 90 MB/s in the other seems
to be the best the old world machines can do. 80 - 90 MB/s on a
theoretical maximum of 132 MB/s isn't too shabby considering all the
other stuff the PCI bus must do to set up a transaction.
Jeff Walther
P.S. Anyone know why Eudora (v. 4.3 in this case) sometimes gives me
an annoying solid bar on the side when I quote text and other times
uses '>' like the gods intended? There doesn't seem to be a
preference to adjust this. It's really annoying to "paste as
quotation" and then go back and add in the > by hand. Earlier
versions of Eudora did this correctly.
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