On Mon, Dec 6, 2010 at 7:04 PM, Gaston Rodriguez
<[email protected]> wrote:
> On 03/12/2010 11:20 p.m., Mike Frysinger wrote:
>>
>> On Friday, December 03, 2010 17:46:29 Gaston Rodriguez wrote:
>>>
>>> I'm using UrJtag to program/erase Actel Fpgas. With previous urjtag (rev
>>> 1737) works fine. The ERASE file is executed in about 53 seconds. But
>>> with latest UrJtag (rev 1868) the player reach the line 110 of the SVF
>>> file and never finishes.
>>
>> please narrow it down.  use git and you can use the automated bisect.
>> -mike
>
> Ok, I think I found where the problem starts... (thanks to "git bisect",
> what a nice tool!)
> The last report is:
>
> 5c3e634a0e4daaf1cf3f6f37ca8a90833a33b046 is the first bad commit
> commit 5c3e634a0e4daaf1cf3f6f37ca8a90833a33b046
> Author: Jie Zhang <[email protected]>
> Date:   Sat Feb 6 00:24:25 2010 +0000
>
>    Optimize TMS clocks for FT2232 cables.

Hello Gaston, have you tried to reduce your cable clock frequency
first? I have written driver fot FT2232H based chip with division
clock turned off and was a bit suprised that the cable did not work...
at first because of the of the high cloock frequency as it turned out
later when i slowed down the cable. The Clock scheduling may be very
helpful for increasing thruput even on a slower interfaces
(esiepcially USB). Please try the "frequency" command after "cable" is
selected and let us know if that helps on optimized code.

Best regards,
Tomek

-- 
CeDeROM, SQ7MHZ, http://www.tomek.cedro.info

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