Good morning to all, As a hobbist CPLD user, I'm trying to implement a low-cost (and obviously, low-speed) jtag cable using commercial development boards (i.e. MSP430 launchpad, Stellaris launchpad, arduino-*); the purpose of this is having a firmware which beginner cpld users can flash onto their random arduino-like board and use to program their CPLD, although in a quite slow way, to understand the principles before needing to buy a commercial programmer (which could never be the case, if they use JTAG once a year). As a first milestone, I would like to be able to play SVF files generated by FPGA development environments.
I think urJTAG could work well for this purpose, as I understand it has a layered structure and so the cable level is independent from the "high level" jtag interpreter. Now, the question is: suppose I have a firmware which receives (via USB) pin states for the TCK, TMS, TRST and TDI pins in a parport fashion, and gives back the TDO state; what should i do to use this simple device as a JTAG adapter with urJTAG? Looking at the source, I suppose I should code a new "cable", which would declare the 11 functions described at http://urjtag.org/book/_drivers.html and then record them into a cable_driver_t struct, and insert it into the *cable_drivers array into tap/cable.c.Is this the correct way to encode a custom jtag device into the software? Or should I implement something different too? (e.g. I see there are "link" drivers, which I suppose to be low-level drivers opening the transaction port) Also, taking as reference tap/cable/byteblaster.c, I see not all of the functions are implemented, but only the most hardware-related ones. Is this feasible? Thank you for your attention and sorry for being this long. -- Simone Baratta ------------------------------------------------------------------------------ _______________________________________________ UrJTAG-development mailing list UrJTAG-development@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/urjtag-development
