Hello, Are there any activities regarding an automatically generated interconnection test (for finding shorts/opens in a circuit) which uses UrJtag?
I am using a commercial tool (Goepel electronics) for boundary scan tests in the company. Then I began looking for a non-commercial / open source tool which can do the same (with an low-cost hardware platform) so everyone at home can use it also. Soon I found UrJtag and OpenOCD as two possible platforms but neither one has a working implementation of this kind of test. In fact, UrJtag seems more convenient for adding such a function: - a working BSDL subsystem exists - a signal structure exists with commands for driving and testing digital values which can be extended by attributes defining the testability of these nets (Are other drivers connected to these nets? Are pull-resistors connected? ...) I would like to know if there is interest in adding such a function or if there are already some ideas on how this should look like? Are there any solutions on the internet which I haven't found looking for it? I have some experience with the commercial solutions and I am ready to spend some time in implementing a kind of interconnection test. Maybe I will be doing this as part of my master thesis, but the main goal should be to make this functionality available to the public. marco ------------------------------------------------------------------------------ Transform Data into Opportunity. Accelerate data analysis in your applications with Intel Data Analytics Acceleration Library. Click to learn more. http://pubads.g.doubleclick.net/gampad/clk?id=278785471&iu=/4140 _______________________________________________ UrJTAG-development mailing list UrJTAG-development@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/urjtag-development
