*Dear vendor partners,*
*Please send the profile to [email protected] <[email protected]> * Number of Openings 5 Duration of Hiring 6 months Detailed job description - Skill Set: “Must to have “ “Nice to have “ *Experience: 4 - 10 Yrs.* *Skill: Low Power ASIC Physical Design, Working experience on Intel Specific RDT flow* *Job Description:* • At least 4 years of experience in the following skills - Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, *clock tree synthesis*), Static Timing Analysis, Formal Verification, Physical Verification(DRC, LVS) and Power Analysis(IR drop, EMIG), Leakage Power Optimization using ICCLR/PTLR flows, on 22nm, 14nm, or lower process technology • Desired Tools Experience: Synopsys ICC flow, Prime Time, Design Compiler, Redhawk, LEC/Formailty, and Caliber. • At least 4 years of experience in Project life cycle activities on development and maintenance projects. • At least 4 years of experience in Physical Design and STA review. • At least 4 years of experience in ASIC development life cycle. • Ability to work in team in diverse/ multiple stakeholder environment Extension Possible Yes Work Location Hillsboro Client Interview / F2F Applicable Yes *Thanks and Regards* *Arvind Nagar* *Email- **[email protected]* <[email protected]> *Direct-408-457-9381 Ext-4008 !! Gtalk- arvindnagar.777 !! Yahoo- * *arvindnagar951* -- You received this message because you are subscribed to the Google Groups "US_IT.Groups" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at http://groups.google.com/group/us_itgroups. For more options, visit https://groups.google.com/d/optout.
