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Today's Topics:
1. Foolish net burning :( (Michael Guidry)
2. How to get access to decimated sample clock and I and Q
samples inside USRP2 FPGA (Jeong-O Jeong)
----------------------------------------------------------------------
Message: 1
Date: Sat, 2 Apr 2011 20:04:21 -0400
From: Michael Guidry <[email protected]>
To: [email protected]
Subject: [USRP-users] Foolish net burning :(
Message-ID: <[email protected]>
Content-Type: text/plain; charset=us-ascii
Hello,
I have unfortunately wrote the wrong firmware to my N210. I wrote the
UHD-images-003-20110317204706-2d906e6/share/uhd/images/usrp2_fw.bin rather than
UHD-images-003-20110317204706-2d906e6/share/uhd/images/usrp_n2xx_fw.bin. The
device has an orange light on the network port.
I have tried the recovery script to no avail. Does anyone have any
suggestions, or any information on recovering from this?
Thanks,
Mike
------------------------------
Message: 2
Date: Sat, 02 Apr 2011 20:48:36 -0400
From: Jeong-O Jeong <[email protected]>
To: [email protected]
Subject: [USRP-users] How to get access to decimated sample clock and
I and Q samples inside USRP2 FPGA
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Hello,
I am trying to implement a simple MSK receiver inside the FPGA of the
USRP2. I already have the verilog module for the receiver, but I am not
sure how to stream the received samples inside the FPGA to my module.
Which signals should I use for the sample clock and for the I and Q samples?
It looks like 'output [31:0] sample' from 'dsp_core_rx0' contains the
decimated I and Q samples, but I am not sure how to get the clock that
runs at the decimated sample rate.
Thank you,
Jeong
------------------------------
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End of USRP-users Digest, Vol 8, Issue 2
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