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Today's Topics:
1. Re: Foolish net burning :( (Nick Foster)
2. Re: How to get access to decimated sample clock and I and Q
samples inside USRP2 FPGA (Matt Ettus)
3. Sensing problem on USRP2 (Massimo Piras)
----------------------------------------------------------------------
Message: 1
Date: Sun, 03 Apr 2011 14:13:46 -0700
From: Nick Foster <[email protected]>
To: Michael Guidry <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Foolish net burning :(
Message-ID: <1301865226.7511.2.camel@crapshoot>
Content-Type: text/plain; charset="UTF-8"
If it's just the firmware you wrote, you should be able to recover by
booting in "safe mode". Just hold down S2 when you plug power into the
N210 and it'll come up using its backup firmware & FPGA images, and you
should be able to load firmware & FPGA images onto the device as normal.
--n
On Sat, 2011-04-02 at 20:04 -0400, Michael Guidry wrote:
> Hello,
>
> I have unfortunately wrote the wrong firmware to my N210. I wrote the
> UHD-images-003-20110317204706-2d906e6/share/uhd/images/usrp2_fw.bin rather
> than UHD-images-003-20110317204706-2d906e6/share/uhd/images/usrp_n2xx_fw.bin.
> The device has an orange light on the network port.
>
> I have tried the recovery script to no avail. Does anyone have any
> suggestions, or any information on recovering from this?
>
> Thanks,
> Mike
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
------------------------------
Message: 2
Date: Sun, 03 Apr 2011 14:17:50 -0700
From: Matt Ettus <[email protected]>
To: Jeong-O Jeong <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] How to get access to decimated sample clock
and I and Q samples inside USRP2 FPGA
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
On 04/02/2011 05:48 PM, Jeong-O Jeong wrote:
> Hello,
>
> I am trying to implement a simple MSK receiver inside the FPGA of the
> USRP2. I already have the verilog module for the receiver, but I am not
> sure how to stream the received samples inside the FPGA to my module.
> Which signals should I use for the sample clock and for the I and Q
> samples?
>
> It looks like 'output [31:0] sample' from 'dsp_core_rx0' contains the
> decimated I and Q samples, but I am not sure how to get the clock that
> runs at the decimated sample rate.
There is no clock that runs at the decimated sample rate. There is a
strobe signal which indicates when the samples are valid. Just use the
samples only when strobe is high.
Matt
------------------------------
Message: 3
Date: Mon, 4 Apr 2011 11:03:17 +0200 (CEST)
From: Massimo Piras <[email protected]>
To: [email protected]
Subject: [USRP-users] Sensing problem on USRP2
Message-ID:
<12094900.240491301907797738.JavaMail.defaultUser@defaultHost>
Content-Type: text/plain;charset="UTF-8"
Hello everyone, I have a question. The USRP2 has problems to work on
the same port in transmission and reception? My work provides that the
two boards do the sensing of a frequency band and then, after a period
of handshaking to find the correct frequency,that one board sends an
image to the other board.
I'm finding that the board does not seem to
work well. In fact, I find the values ??of sensing very far from
reality as measured by the spectrum analyzer. Any suggestions?
Thank
you!!
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------------------------------
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End of USRP-users Digest, Vol 8, Issue 3
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