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Today's Topics:
1. N210 with XCVR2450 Receives only Noise (Mike Lucas)
2. Re: N210 with XCVR2450 Receives only Noise (Marcus D. Leech)
3. Gain Distribution for RFX900 (Gonzalo Flores De La Parra)
4. Addressing custom logic in fpga (Diego Montemayor)
5. Re: Addressing custom logic in fpga (Marcus D. Leech)
6. Re: Addressing custom logic in fpga (Ian Buckley)
7. Re: Addressing custom logic in fpga (Diego Montemayor)
8. Re: Gain Distribution for RFX900 (Josh Blum)
9. HELP: the relationship between bandwidth and the sample rate?
(zhangfan)
10. Re: Addressing custom logic in fpga (Johnathan Corgan)
11. Open BTS: handovers (ayiesha murtaza)
12. Re: Open BTS: handovers (Nowlan, Sean)
----------------------------------------------------------------------
Message: 1
Date: Tue, 12 Feb 2013 17:00:39 -0500
From: Mike Lucas <[email protected]>
To: [email protected]
Subject: [USRP-users] N210 with XCVR2450 Receives only Noise
Message-ID:
<calywa+x3zgzmgh03kqybhbjtvr3+jd+vci4uangc4j1akd7...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hello All:
I'm just getting my feet wet with N210 via gnuradio-companion. I've been
unsuccessfully trying to confirm my setup by receiving nearby 2.4GHz
802.11g signals, and displaying them in an FFT. I've tried various BWs,
center frequencies, and connecting to both antenna ports but, thusfar, I'm
only observing noise in the FFT. A typical GRC diagram I've been using is
attached.
Feels like I'm making a stupid/n00b mistake here, but i'm a little at a
loss... perhaps incorrect FW?
I'm running ubuntu 12.04LTS with GRC 3.6.3. I upgraded the firmware,
having been prompted to do so, using the usrp_n2xx_net_burner.py script to
FW: usrp_n210_fw.bin and FPGA: usrp_n210_r4_fpga.bin . The images I used
were bundled in the uhd-images_003.005.001-release tarball.
Running uhd_usrp_probe gives:
linux; GNU C++ version 4.6.3; Boost_104601; UHD_003.005.001-release
-- Opening a USRP2/N-Series device...
-- Current recv frame size: 1472 bytes
-- Current send frame size: 1472 bytes
_____________________________________________________
/
| Device: USRP2 / N-Series Device
| _____________________________________________________
| /
| | Mboard: N210r4
| | hardware: 2577
| | mac-addr: a0:36:fa:38:33:59
| | ip-addr: 192.168.10.2
| | subnet: 255.255.255.255
| | gateway: 255.255.255.255
| | gpsdo: none
| | serial: E5R23NAUP
| | FW Version: 12.3
| | FPGA Version: 10.0
| |
| | Time sources: none, external, _external_, mimo
| | Clock sources: internal, external, mimo
| | Sensors: mimo_locked, ref_locked
| | _____________________________________________________
| | /
| | | RX DSP: 0
| | | Freq range: -50.000 to 50.000 Mhz
| | _____________________________________________________
| | /
| | | RX DSP: 1
| | | Freq range: -50.000 to 50.000 Mhz
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: XCVR2450, XCVR2450 - r2.1 (0x0061)
| | | Serial: E5R15YBXX
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: XCVR2450 RX
| | | | Antennas: J1, J2
| | | | Sensors: lo_locked, rssi
| | | | Freq range: 2400.000 to 6000.000 Mhz
| | | | Gain range LNA: 0.0 to 30.5 step 15.0 dB
| | | | Gain range VGA: 0.0 to 62.0 step 2.0 dB
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p44
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | | | Gain range fine: 0.0 to 0.5 step 0.1 dB
| | _____________________________________________________
| | /
| | | TX DSP: 0
| | | Freq range: -250.000 to 250.000 Mhz
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: XCVR2450 (0x0060)
| | | Serial: E5R15YBXX
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: XCVR2450 TX
| | | | Antennas: J1, J2
| | | | Sensors: lo_locked
| | | | Freq range: 2400.000 to 6000.000 Mhz
| | | | Gain range VGA: 0.0 to 30.0 step 0.5 dB
| | | | Gain range BB: 0.0 to 5.0 step 1.5 dB
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9777
| | | | Gain Elements: None
Thanks a lot for your help.
-Mike
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Message: 2
Date: Tue, 12 Feb 2013 17:15:17 -0500
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] N210 with XCVR2450 Receives only Noise
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
> Hello All:
> I'm just getting my feet wet with N210 via gnuradio-companion. I've
> been unsuccessfully trying to confirm my setup by receiving nearby
> 2.4GHz 802.11g signals, and displaying them in an FFT. I've tried
> various BWs, center frequencies, and connecting to both antenna ports
> but, thusfar, I'm only observing noise in the FFT. A typical GRC
> diagram I've been using is attached.
> Feels like I'm making a stupid/n00b mistake here, but i'm a little at
> a loss... perhaps incorrect FW?
> I'm running ubuntu 12.04LTS with GRC 3.6.3. I upgraded the firmware,
> having been prompted to do so, using the usrp_n2xx_net_burner.py
> script to FW: usrp_n210_fw.bin and FPGA: usrp_n210_r4_fpga.bin . The
> images I used were bundled in the uhd-images_003.005.001-release tarball.
The main spectral lobe of an 802.11g signal is about 10Mhz wide, and
very noise-like.
Make sure you're on the correct frequency, and see if unplugging your
access point causes teh noise floor to come up and down.
--
Marcus Leech
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
------------------------------
Message: 3
Date: Tue, 12 Feb 2013 18:37:41 -0600
From: Gonzalo Flores De La Parra <[email protected]>
To: [email protected]
Subject: [USRP-users] Gain Distribution for RFX900
Message-ID:
<CACWyxXAyqQt6PhqS6R5Fwro+GHo2WBXoDGOcEhGOgsw=f2c...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi list..
i work with USRPN210+WBX and RFX900, i read in a previous topic how the
gain is distributed for the first case but i would like to know where can i
check the way gain is distributed in other DB's or at least in the RFX900.
Also, to values of the gain range for the DB are always in dB? what power
is that? how can measure it or calculate it?
Thanks in advanced
--
Ing. Gonzalo Flores De La Parra
Electr?nica en Comunicaciones
Universidad Aut?noma Metropolitana
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Message: 4
Date: Tue, 12 Feb 2013 21:03:41 -0500
From: Diego Montemayor <[email protected]>
To: [email protected]
Subject: [USRP-users] Addressing custom logic in fpga
Message-ID:
<canrcev2-vxd5avelvs6xw5wdqn2dhqgwzp_gzcuuohwrrxt...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hello,
I'm working on a project that involves modifying the fpga contents and
adding an additional DDC that works in parallel to the first DSP block.
The idea would be to sample the same data at two different center
frequencies. I'd like to be able to program these frequencies separately
through the API but am worried there may not be enough room in the address
map. Is there a simple way to do this without making many changes to the
API? Would it be possible to configure them under the same address?
Thanks,
Diego
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Message: 5
Date: Tue, 12 Feb 2013 21:16:34 -0500
From: "Marcus D. Leech" <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Addressing custom logic in fpga
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
> Hello,
>
> I'm working on a project that involves modifying the fpga contents and
> adding an additional DDC that works in parallel to the first DSP
> block. The idea would be to sample the same data at two different
> center frequencies. I'd like to be able to program these frequencies
> separately through the API but am worried there may not be enough room
> in the address map. Is there a simple way to do this without making
> many changes to the API? Would it be possible to configure them under
> the same address?
>
> Thanks,
>
> Diego
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Which base platform?
There's already dual-DDC support in some of the platforms, the N2XX in
particular.
--
Principal Investigator
Shirleys Bay Radio Astronomy Consortium
http://www.sbrac.org
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Message: 6
Date: Tue, 12 Feb 2013 22:40:00 -0800
From: Ian Buckley <[email protected]>
To: "[email protected] forum" <[email protected]>
Subject: Re: [USRP-users] Addressing custom logic in fpga
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
On Feb 12, 2013, at 6:16 PM, Marcus D. Leech <[email protected]> wrote:
>> Hello,
>>
>> I'm working on a project that involves modifying the fpga contents and
>> adding an additional DDC that works in parallel to the first DSP block. The
>> idea would be to sample the same data at two different center frequencies.
>> I'd like to be able to program these frequencies separately through the API
>> but am worried there may not be enough room in the address map. Is there a
>> simple way to do this without making many changes to the API? Would it be
>> possible to configure them under the same address?
>>
>> Thanks,
>>
>> Diego
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
> Which base platform?
>
> There's already dual-DDC support in some of the platforms, the N2XX in
> particular.
>
>
>
> --
> Principal Investigator
> Shirleys Bay Radio Astronomy Consortium
> http://www.sbrac.org
Diego,
As Marcus already pointed out, most of the current USRP's already have code
that supports 2 independent receive DSP's including DDC's.
If you do ever add further logic to the Verilog and find you are running short
off address space, then it is quite simple to add a new settings_bus bridge,
identical to the existing one to one of the unused Wishbone bus slave locations
so that you have an entire new settings bus to use.
-Ian
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 7
Date: Wed, 13 Feb 2013 01:56:53 -0500
From: Diego Montemayor <[email protected]>
To: Ian Buckley <[email protected]>
Cc: "[email protected] forum" <[email protected]>
Subject: Re: [USRP-users] Addressing custom logic in fpga
Message-ID:
<CANRCeV1-jByTftp7cMAqdrXaUYfDs1Q-bqjvdgrQCfA=82l...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
This would be for the N210. I know there are two DDCs available but our
design could still benefit from additional ones. What changes would I need
to make in the host side to access the new DDCs? Could it be as simple as
initializing the USRP with an additional DDC and adding the new addresses
in the relevant files?
ie.
// create rx dsp control objects
_mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(_mbc[mb].wbiface,
U2_REG_SR_ADDR(SR_RX_DSP0), U2_REG_SR_ADDR(SR_RX_CTRL0), USRP2_RX_SID_BASE
+ 0, true));
_mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(_mbc[mb].wbiface,
U2_REG_SR_ADDR(SR_RX_DSP1), U2_REG_SR_ADDR(SR_RX_CTRL1), USRP2_RX_SID_BASE
+ 1, true));
// New DDC added here
// SR_RX_DSP2 and SR_RX_CTRL2 are declared accordingly
_mbc[mb].rx_dsps.push_back(rx_dsp_core_200::make(_mbc[mb].wbiface,
U2_REG_SR_ADDR(SR_RX_DSP2), U2_REG_SR_ADDR(SR_RX_CTRL2), USRP2_RX_SID_BASE
+ 2, true));
On Wed, Feb 13, 2013 at 1:40 AM, Ian Buckley <[email protected]> wrote:
>
> On Feb 12, 2013, at 6:16 PM, Marcus D. Leech <[email protected]> wrote:
>
> Hello,
>
> I'm working on a project that involves modifying the fpga contents and
> adding an additional DDC that works in parallel to the first DSP block.
> The idea would be to sample the same data at two different center
> frequencies. I'd like to be able to program these frequencies separately
> through the API but am worried there may not be enough room in the address
> map. Is there a simple way to do this without making many changes to the
> API? Would it be possible to configure them under the same address?
>
> Thanks,
>
> Diego
>
>
> _______________________________________________
> USRP-users mailing
> [email protected]http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
> Which base platform?
>
> There's already dual-DDC support in some of the platforms, the N2XX in
> particular.
>
>
>
> --
> Principal Investigator
> Shirleys Bay Radio Astronomy Consortiumhttp://www.sbrac.org
>
> Diego,
> As Marcus already pointed out, most of the current USRP's already have
> code that supports 2 independent receive DSP's including DDC's.
> If you do ever add further logic to the Verilog and find you are running
> short off address space, then it is quite simple to add a new settings_bus
> bridge, identical to the existing one to one of the unused Wishbone bus
> slave locations so that you have an entire new settings bus to use.
> -Ian
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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Message: 8
Date: Wed, 13 Feb 2013 02:22:45 -0600
From: Josh Blum <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] Gain Distribution for RFX900
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1
On 02/12/2013 06:37 PM, Gonzalo Flores De La Parra wrote:
> Hi list..
> i work with USRPN210+WBX and RFX900, i read in a previous topic how the
> gain is distributed for the first case but i would like to know where can i
> check the way gain is distributed in other DB's or at least in the RFX900.
For reference:
"""
So when setting the overall RX gain, the gain is first distributed to
the RF frontend, then to the ADC. For TX, the gain is first distributed
to the DAC, then to the RF frontend.
"""
This applies to all of the daughterboards. ,RFX though has no transmit
gain on the daughterboard:
http://files.ettus.com/uhd_docs/manual/html/dboards.html
Also, you can also use the API to set gain elements individually, in
case the automatic distribution is not desirable. Gain elements have
name like "PGA0", you can use this in the name field for the set_rx_gain
method.
> Also, to values of the gain range for the DB are always in dB? what power
> is that? how can measure it or calculate it?
> Thanks in advanced
The values are always in dB.
Its best to calibrate the absolute level with a test tone slightly off
the desired center frequency of interest.
-josh
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
------------------------------
Message: 9
Date: Wed, 13 Feb 2013 17:32:15 +0800
From: zhangfan <[email protected]>
To: <[email protected]>
Subject: [USRP-users] HELP: the relationship between bandwidth and the
sample rate?
Message-ID: <[email protected]>
Content-Type: text/plain; charset="gb2312"
Hallo everyone,
i am using USRP N210 and daughterboard RFX2400. Right now i have some problems
with the bandwidth. I have read the specification of the daughterboard RFX2400,
it has 25MHz bandwidth.
when i change the sample rate in the configuration of the receiver block, the
bandwidth of
the signal i received changes also. Is that correct? i am a little confused.
And if i want to
receive a signal with large bandwidth, i have to increase the sample rate, but
what i
receive would just be background noise.
kann someone help me, any suggestions would be great!
Thanks in advance
Greetings
Fan
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Message: 10
Date: Wed, 13 Feb 2013 05:57:56 -0800
From: Johnathan Corgan <[email protected]>
To: Ian Buckley <[email protected]>
Cc: "[email protected] forum" <[email protected]>
Subject: Re: [USRP-users] Addressing custom logic in fpga
Message-ID:
<caloxbzuozpetk7-j0p03exxnvddcyq+dub8h6i1_lvjusjz...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
On Tue, Feb 12, 2013 at 10:40 PM, Ian Buckley <[email protected]> wrote:
> If you do ever add further logic to the Verilog and find you are running
> short off address space, then it is quite simple to add a new settings_bus
> bridge, identical to the existing one to one of the unused Wishbone bus
> slave locations so that you have an entire new settings bus to use.
>
There is already a dedicated settings bus in place specifically for use in
custom designs, which allows the user to create up to 256 32-bit write-only
configuration registers that exist outside the address space of the
standard settings bus.
In the top level module (e.g., u2plus_core.v), there are wires
'set_addr_user', 'set_data_user', and 'set_stb_user', with the same
semantics as the standard configuration bus. To use these in a custom
design, one creates new instances of 'settings_reg' but connects their
inputs to this set of wires instead.
To initiate a write cycle, from the host UHD interface one issues a call to:
void set_user_register(const boost::uint8_t addr, const boost::uint32_t
data, size_t mboard = ALL_MBOARDS)
...from an instance of uhd::usrp::multi_usrp. This call is also part of
the GNU Radio UHD source and sink blocks.
Johnathan
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Message: 11
Date: Wed, 13 Feb 2013 19:42:00 +0500
From: ayiesha murtaza <[email protected]>
To: [email protected]
Subject: [USRP-users] Open BTS: handovers
Message-ID:
<CAC2Y=ckhvnfza6rrkh8lbqy+++wylg6twe1rbk8x6irgz1n...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Has anyone implemented handovers using public release of OpenBTS? what
editing in the code was needed?
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Message: 12
Date: Wed, 13 Feb 2013 14:55:27 +0000
From: "Nowlan, Sean" <[email protected]>
To: ayiesha murtaza <[email protected]>,
"[email protected]" <[email protected]>
Subject: Re: [USRP-users] Open BTS: handovers
Message-ID: <195933287DC65748BA7AE867BA8E430B623C68EE@apatlisdmbx02>
Content-Type: text/plain; charset="iso-8859-1"
Please use the OpenBTS list for OpenBTS questions. They will be able to give
you more specific help.
[email protected]
Good luck.
--sean
________________________________
From: USRP-users [[email protected]] on behalf of ayiesha
murtaza [[email protected]]
Sent: Wednesday, February 13, 2013 9:42 AM
To: [email protected]
Subject: [USRP-users] Open BTS: handovers
Has anyone implemented handovers using public release of OpenBTS? what editing
in the code was needed?
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Subject: Digest Footer
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------------------------------
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******************************************
