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Today's Topics:
1. Echo Cancellation for USRP? (Alex Zhang)
2. Fifo ctrl timed out looking for acks (Paul Pruitt)
3. Re: USRP Tx interpolation factor (Mike McLernon)
4. Building the UHD driver in Windows 7, Visual Studio 2010
ultimate environment (Sammy Kolpinizki)
5. Changing FPGA Code in USRP N210 (Jinu Jayachandran)
6. Re: Changing FPGA Code in USRP N210 (Johnathan Corgan)
7. Re: Changing FPGA Code in USRP N210 (Ben Reynwar)
8. Re: Building the UHD driver in Windows 7, Visual Studio 2010
ultimate environment (Nicholas Corgan)
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Message: 1
Date: Thu, 14 Feb 2013 12:16:44 -0600
From: Alex Zhang <[email protected]>
To: gnuradio mailing list <[email protected]>, usrp-users
<[email protected]>
Subject: [USRP-users] Echo Cancellation for USRP?
Message-ID:
<CA+FEAndZ=zsyj-vas1+bta8onamvhha2p-_nnkk9ccqqk_-...@mail.gmail.com>
Content-Type: text/plain; charset="windows-1252"
Hello Gurus,
My duplex system is using only one frequency but different time slot to let
two USRP exchange data. But from the observed receiving waveforms, I found
that the received signal is very high and causes the jitter if the receiver
keeps receiving its own transmitted signal within its own time slot. This
jitter could impact the subsequent time slot for other transmitter, by a
tail.
I want to add something like echo cancellation to remove this side-effect.
Before that I am wondering if any has done the similar thing. Also, I
don't think the pure software method can solve this problem. Do we have any
hardware support for this transmitting close loop issue?
Best Regards,
--
Alex,
*Dreams can come true ? just believe.*
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Message: 2
Date: Thu, 14 Feb 2013 14:49:40 -0500
From: Paul Pruitt <[email protected]>
To: [email protected]
Subject: [USRP-users] Fifo ctrl timed out looking for acks
Message-ID:
<caaj-vfbsq0ap4hxd-mekzwd4outxbkcfmgzgnf7jxyyx25q...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
I'm getting this exception, thrown from
usrp2_fifo_ctrl_impl::wait_for_acks, sometimes after several hours of
operation.
The device is an N210 with UHD version 003:005.000-26-gb65a3924 on a laptop
under CentOS 6.3 64-bit. I'm collecting 100 ms duration streams from both
channels at 10 MSPS (each) every 250 ms.
As an experiment, I increased ACK_TIMEOUT from 0.5 s to 5.5 s. The
exception still occurred. No ethernet errors or dropped packets are
reported by ifconfig. I am running as root and verified the threads are
running at realtime priority with htop. The frame sizes, recv_frame_size
and send_frame_size, are set to 4095 bytes. Kernel rx/tx socket buffers are
5MB.
Any idea what might be causing this?
Is it safe to catch the exception and keep going? If I restart my program
after the exception, the USRP works fine.
Thanks,
Paul
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Message: 3
Date: Thu, 14 Feb 2013 21:43:05 +0000
From: Mike McLernon <[email protected]>
To: Invizible Box <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] USRP Tx interpolation factor
Message-ID:
<e3879be9a282cb45aab7ce258a9ae48f218a1...@exmb-01-ah.ad.mathworks.com>
Content-Type: text/plain; charset="us-ascii"
Hi Ciao,
Several points:
1. The Simulink sample time has no relationship to wall clock time. It
is a simulation artifact.
2. Having said that, it aids sanity to set the Simulink sample time to be
consistent with the USRP D/A or A/D. Those data converters run at 100 MHz.
3. If you have a sample time of 1e-6, it corresponds to a sample rate of
1e6. You would use an interpolation factor of 100 to achieve that consistency
between Simulink and the USRP D/A.
4. The insertion of a Buffer block between your data source and the SDRu
Transmitter block will change the Simulink frame time. This frame time is
(sample time * frame length). The underlying Simulink sample time is
unchanged, but if you turn on sample time colors for the model, it will show
the frame time, not the sample time.
Hth,
Mike
From: USRP-users [mailto:[email protected]] On Behalf Of
Invizible Box
Sent: Thursday, February 14, 2013 11:52 AM
To: [email protected]
Subject: [USRP-users] USRP Tx interpolation factor
Hello everyone,
I am new to the USRP world. I am working on USRP n210.
I want to implement a transmitter using simulink-matlab. I have I/Q data saved
in a file which I read into simulink and I have a sample time of 1e-6 at the
''From Workspace'' block.
I want to know how we select the interpolation factor in the sdru Tx block and
how it effects the input sample time. How will it change if i put a buffer
between the sdru tx and my source data.
Thanking in advance,
Ciao
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Message: 4
Date: Fri, 15 Feb 2013 11:22:55 +0200
From: "Sammy Kolpinizki" <[email protected]>
To: <[email protected]>
Subject: [USRP-users] Building the UHD driver in Windows 7, Visual
Studio 2010 ultimate environment
Message-ID: <[email protected]>
Content-Type: text/plain; charset="us-ascii"
Hi.
I'm new to the forum and to the USRP.
I'm attempting to build the UHD under windows environment.
I tried following the instructions in the build guide
<http://files.ettus.com/uhd_docs/manual/html/build.html> but I encountered
various problems using CMake.
Say I succeed in working with CMake, what should I get at the end? A working
visual studio project?
I tried to build a project manually by adding source/header files to a
custom made project, but I'm not sure
Which #defines I should enable.
Is there any easy way to create a visual studio project?
Thanks,
Sammy.
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Message: 5
Date: Fri, 15 Feb 2013 15:01:50 +0530
From: Jinu Jayachandran <[email protected]>
To: [email protected]
Subject: [USRP-users] Changing FPGA Code in USRP N210
Message-ID:
<CAKmcSyZ+WM3Xuj=9n3xUBHH84h27V8LjhttbpdQ2jEt=tjf...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hi,
I am trying to implement an FFT algorithm in USRP N210 R4 FPGA. I would
like to know if the procedure I am following to build the FPGA image is
correct. The procedure is as follows
1) Downloaded the images from
http://code.ettus.com/redmine/ettus/projects/uhd/repository
2) I have edited the make file in the images folder to make images only for
N series firmware and N210 FPGA
3) Then I did a 'make images' in the image folder
4) It generated a .bin files for firmware and FPGA in /images/images folder
I am facing the following problems
1) The building of the fpga image took around 30 minutes in my machine. So
whenever I edit the FPGA code I should wait for 30 minutes before I want to
test if it is working properly. Is this the normal time it takes to build
?. Can I reduce the time to build image in some way?
2) I would like to know where to put by FFT verilog code for the receiver
in the FPGA?. From the code review I have done, my understanding is to put
the code in /usrp2/top/N2x0/u2plus_core.v. And I need to get the sample_rx0
value and strobe_rx0 values from the ddc_chain block as input to my FFT
block and give the output to vita_rx_chain. Is my understanding correct ?.
(I tried to implement a simple code by taking the sample_rx0 from
ddc_chain, modify it and sent to vita_rx_chain. Then i used the narrowband
example in the gnuradio to check if there is any change in data. But there
is no change and sometimes the receiver doesn't receive at all).
Please help
Thanks and Regards
Jinu
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Message: 6
Date: Fri, 15 Feb 2013 07:01:01 -0800
From: Johnathan Corgan <[email protected]>
To: Jinu Jayachandran <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Changing FPGA Code in USRP N210
Message-ID:
<caloxbzssr+pi0r9iboz0hivnw_r8xprxi0ah6pt7ywseokr...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
On Fri, Feb 15, 2013 at 1:31 AM, Jinu Jayachandran <
[email protected]> wrote:
> 1) The building of the fpga image took around 30 minutes in my machine. So
> whenever I edit the FPGA code I should wait for 30 minutes before I want to
> test if it is working properly. Is this the normal time it takes to build
> ?. Can I reduce the time to build image in some way?
>
This is about right. Currently, make does a full synthesis and
place-and-route each time. It is theoretically possible to implement
incremental synthesis using the Xilinx tools, but that would be a large
amount of work and the current code organization would need to change
considerably.
For this reason I recommend creating a Verilog testbench around the portion
of the logic you are modifying and do as much development and verification
in simulation as possible before going to synthesis. At synthesis time you
are then usually focused on debugging timing closure issues but not
correctness of function.
> 2) I would like to know where to put by FFT verilog code for the receiver
> in the FPGA?. From the code review I have done, my understanding is to put
> the code in /usrp2/top/N2x0/u2plus_core.v. And I need to get the sample_rx0
> value and strobe_rx0 values from the ddc_chain block as input to my FFT
> block and give the output to vita_rx_chain. Is my understanding correct ?.
> (I tried to implement a simple code by taking the sample_rx0 from
> ddc_chain, modify it and sent to vita_rx_chain. Then i used the narrowband
> example in the gnuradio to check if there is any change in data. But there
> is no change and sometimes the receiver doesn't receive at all).
>
This is a good place to do it. Alternatively, you can modify ddc_chain.v
to add your logic to the end of the RX processing. Either way, however, it
is important to understand the function of the 'run' input from the
rx_control module. This is directly controlled by the UHD logic to gate
when to stream samples over sample_rx0/strobe_rx0, and acts as a sort of
enable for much of the ddc_chain logic. If you modify the logic you will
have to ensure that anything inserted between ddc_chain and rx_control
manages this properly, and also accounts for any pipeline delay within your
new logic.
Johnathan
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Message: 7
Date: Fri, 15 Feb 2013 08:44:51 -0700
From: Ben Reynwar <[email protected]>
To: Jinu Jayachandran <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Changing FPGA Code in USRP N210
Message-ID:
<cahxoyponty4t1ghjt7jkq6oindbmrf_d8x7dzbzteq0wbrd...@mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1
I've had a crack at getting an FFT working on the B100 FPGA. It's not
working yet, but it might still be useful to check out.
The code is at:
https://github.com/benreynwar/fpga-sdrlib
I do as much debugging on possible using the Icarus simulator and use
MyHDL to interface with it so I can write my QA code in python.
Ben
On Fri, Feb 15, 2013 at 2:31 AM, Jinu Jayachandran
<[email protected]> wrote:
> Hi,
>
> I am trying to implement an FFT algorithm in USRP N210 R4 FPGA. I would
> like to know if the procedure I am following to build the FPGA image is
> correct. The procedure is as follows
>
> 1) Downloaded the images from
> http://code.ettus.com/redmine/ettus/projects/uhd/repository
> 2) I have edited the make file in the images folder to make images only for
> N series firmware and N210 FPGA
> 3) Then I did a 'make images' in the image folder
> 4) It generated a .bin files for firmware and FPGA in /images/images folder
>
> I am facing the following problems
>
> 1) The building of the fpga image took around 30 minutes in my machine. So
> whenever I edit the FPGA code I should wait for 30 minutes before I want to
> test if it is working properly. Is this the normal time it takes to build ?.
> Can I reduce the time to build image in some way?
>
> 2) I would like to know where to put by FFT verilog code for the receiver in
> the FPGA?. From the code review I have done, my understanding is to put the
> code in /usrp2/top/N2x0/u2plus_core.v. And I need to get the sample_rx0
> value and strobe_rx0 values from the ddc_chain block as input to my FFT
> block and give the output to vita_rx_chain. Is my understanding correct ?.
> (I tried to implement a simple code by taking the sample_rx0 from
> ddc_chain, modify it and sent to vita_rx_chain. Then i used the narrowband
> example in the gnuradio to check if there is any change in data. But there
> is no change and sometimes the receiver doesn't receive at all).
>
> Please help
>
> Thanks and Regards
> Jinu
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
------------------------------
Message: 8
Date: Fri, 15 Feb 2013 08:14:20 -0800
From: Nicholas Corgan <[email protected]>
To: Sammy Kolpinizki <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Building the UHD driver in Windows 7, Visual
Studio 2010 ultimate environment
Message-ID:
<CAGCyN2PhbYGpsrZJwz+csC=at+mo539qdeb9zeyf8-hsd0i...@mail.gmail.com>
Content-Type: text/plain; charset="windows-1252"
When you run CMake, you will get a complete Visual Studio solution. Just
open this solution in MSVC, and you will be able to build it.
On Fri, Feb 15, 2013 at 1:22 AM, Sammy Kolpinizki <[email protected]>wrote:
> Hi.****
>
> ** **
>
> I?m new to the forum and to the USRP.****
>
> I?m attempting to build the UHD under windows environment. ****
>
> I tried following the instructions in the build
> guide<http://files.ettus.com/uhd_docs/manual/html/build.html>but I
> encountered various problems using CMake.
> ****
>
> ** **
>
> Say I succeed in working with CMake, what should I get at the end? A
> working visual studio project?****
>
> I tried to build a project manually by adding source/header files to a
> custom made project, but I?m not sure ****
>
> Which #defines I should enable.****
>
>
> Is there any easy way to create a visual studio project?****
>
> ** **
>
> Thanks,****
>
> Sammy.****
>
> ** **
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
--
Nicholas Corgan
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