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Today's Topics:
1. X300 Becomes unresponsive after an exception throw
(Robert Palumbo)
2. Re: Signal multiplier access (Ian Buckley)
3. Re: Achieving higher sampling rates with the N210 for
multi-constellation GNSS record-playback (Adrian Martinez Gomez)
----------------------------------------------------------------------
Message: 1
Date: Wed, 9 Apr 2014 15:21:39 -0400
From: Robert Palumbo <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] X300 Becomes unresponsive after an exception
throw
Message-ID:
<CAKwzk9yJW2tFOM0Op0KBjXFXX97xJarjOh1Q-=WdehV=3_=q...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Hey All,
Can anyone confirm a behavior for me?
I'm using an X300, and I find that whenever my application throws an error
from the UHD, I can no longer ping or communicate to the device afterwards.
I'm required to do a hard power cycle before I can begin communicating with
the device again.
Rob
--
Robert A Palumbo
[email protected]
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Message: 2
Date: Wed, 9 Apr 2014 12:29:12 -0700
From: Ian Buckley <[email protected]>
To: Vladica Sark <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Signal multiplier access
Message-ID: <[email protected]>
Content-Type: text/plain; charset=iso-8859-1
Vladica,
We deleberatly do not expose direct gain control for this multiplier in the UHD
API.
This gain block is used to compensate for variable algorithmic gain in other
elements on the signal chain and the sample format used in the transport. We
leave it configured to maximize dynamic range available to the application.
You'll find the applicable code in host/lib/usrp/cores/*_dsp_core_*.cpp; search
for the private variables _scaling_adjustment and _dsp_extra_scaling.
-Ian
On Apr 9, 2014, at 5:28 AM, Vladica Sark <[email protected]> wrote:
> Hi again,
>
> Just implemented it, but probably it is a good option to have it in the
> next releases of UHD, for direct access.
>
> BR,
> Vladica
>
>
> On 04/09/2014 02:11 PM, Vladica Sark wrote:
>> Hi Marcus,
>>
>> Thanks for the fast reply, I was searching for a direct access, but it
>> seems there is no such function in UHD, accessible from the user side.
>> Anyway, I have already made a function for direct access of the
>> registers, so it seems I have to use it.
>>
>> BR,
>> Vladica
>>
>>
>> On 04/09/2014 02:01 PM, Marcus M?ller wrote:
>>> Hi Vladica,
>>>
>>> maybe I can be of help: Searching the UHD source code tree using
>>> "git grep SR_RX_DSP0" shows occurrences in different device
>>> drivers; maybe you can refer to these implementations of register
>>> accesses. How register access is done depends on what device you
>>> are using, so stick to the same device line.
>>>
>>> Greetings, Marcus
>>>
>>> On 09.04.2014 13:53, Vladica Sark wrote:
>>>> Hi there,
>>>
>>>> Does anybody knows how to access the signal multiplier
>>>> "scale_factor" in the ddc_chain, address SR_RX_DSP0+1, directly
>>>> from UHD driver?
>>>
>>>> BR, Vladica
>>>
>>>> _______________________________________________ USRP-users
>>>> mailing list [email protected]
>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>>>
>>>
>>> _______________________________________________ USRP-users mailing
>>> list [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
------------------------------
Message: 3
Date: Thu, 10 Apr 2014 15:43:17 +0200
From: Adrian Martinez Gomez <[email protected]>
To: Ian Buckley <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] Achieving higher sampling rates with the
N210 for multi-constellation GNSS record-playback
Message-ID:
<cabefxybzprvbvblpef7akh6ij4m5dqz58kjyx_p3eoebfth...@mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"
Thanks Ian,
I finally managed to get it working (thanks for your help and the one of
the others).
I generated the FPGA image, and was trying to burn it with the net burner
tool:
http://files.ettus.com/uhd_docs/manual/html/usrp2.html#load-the-images-onto-the-on-board-flash-usrp-n-series-only
I didn't modify anything on the FPGA source code, only generated it myself
with Xilinx.
After that my USRP stopped working, and I have to power in safe-mode with
the S2 button described under "Device recovery and bricking".
Now I have tried to give my USRP a new IP address, since it is not beeing
recognized when running uhd_find_devices, by running:
cd /usr/local/lib/uhd/utils
sudo ./usrp2_recovery.py --ifc=eth0 --new-ip=192.168.20.2
The output seems correct, but when trying to ping the device or run
uhd_find_devices there is no success.
Any ideas on how to recover my USRP N210?
On Mon, Apr 7, 2014 at 4:29 PM, Ian Buckley <[email protected]> wrote:
> The issue you are seeing is not caused by the FPGA code but is a problem
> with the Xilinx tools. ISE is failing to find an executable library that is
> supplied with the tools. Have you run /opt/Xilinx/12.2/ISE_DS/settings64.sh
> (This is the default install location)?
> -Ian
>
> On Apr 7, 2014, at 1:27 AM, Adrian Martinez Gomez <[email protected]>
> wrote:
>
> Hello all,
>
> although I know this is probably no USRP specific question, but rather a
> Xilinx one, I would want to know the opinion of the ones of you who have
> worked with the FPGA code.
>
> What I am trying to do is just to generate the bin file for the FPGA for
> the USRP N210 myself, using the ISE Suite Edition (12.2 version; with 30
> day trial license).
> I followed the instruction on the README.txt on the fpga folder of
> https://github.com/EttusResearch/uhd/tree/master/fpga
> When running "make -f Makefile.N210R4 bin" I get the following in the
> build.log file, and an empty .bin build:
> *Mapping completed. *
>
> *See MAP report file u2plus_map.mrp for details.*
>
> */opt/Xilinx/12.2/ISE_DS/ISE/bin/lin64/unwrapped/ma**p: symbol lookup
> error: /opt/Xilinx/12.2/ISE_DS/ISE//lib/lin64/libXst_Core**.so: undefined
> symbol: _ZN5antlr6BitSetD1Ev*
> * Process "Map" failed*
>
> Did someone have the same issue? Some ideas on what might have gone wrong?
> The FPGA code is unmodified, I only wanted to be able to generate the FPGA
> image myself (for future modifications).
>
> Thanks in advance!
>
> P.S. attached you will find my build.log as well as my u2plus_map.mrp (in
> case it helps)
>
> build.log<https://docs.google.com/file/d/0B1MBvlNk1q2sbkRHaWhkZ1lYRnp2bXgzY2F1S212TjBkby0w/edit?usp=drive_web>
>
>
> u2plus_map.mrp<https://docs.google.com/file/d/0B1MBvlNk1q2sdWNoVFBYdWRlWlFMT1M5aTFseW9sTnkyQmhR/edit?usp=drive_web>
>
>
> On Thu, Apr 3, 2014 at 4:42 PM, Adrian Martinez Gomez <
> [email protected]> wrote:
>
>> At the end another NIC (already on the PC, just another port) worked just
>> fine.
>>
>> @Marcus. For the time being I will stick with trying to do the reduction
>> on the FPGA. The network bandwidth would be also a motivation for doing it
>> this way.
>>
>>
>> On Thu, Apr 3, 2014 at 2:14 PM, Martin Braun <[email protected]>wrote:
>>
>>> On 04/02/2014 03:20 PM, Adrian Martinez Gomez wrote:
>>> > Quick update:
>>> > I achieved the 25Msps and sc16 as well as 50Msps and sc8 with some NIC
>>> > work. Now both rx and tx work fine.
>>>
>>> Hi Adrian,
>>>
>>> what did you do? Did you try another NIC, or do some configuration?
>>>
>>> Martin
>>>
>>>
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected]
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>>
>>
>>
> _______________________________________________
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>
>
>
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