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Today's Topics:
1. X300 ,internal PPS was not detected ? (ORN via USRP-users)
2. Re: X300 ,internal PPS was not detected ?
(Michael West via USRP-users)
----------------------------------------------------------------------
Message: 1
Date: Fri, 25 Apr 2014 18:36:23 +0200
From: ORN via USRP-users <[email protected]>
To: [email protected]
Subject: [USRP-users] X300 ,internal PPS was not detected ?
Message-ID: <[email protected]>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed
Hi
with the latest image "usrp_x300_fpga_HGS.bin" (from 21 april ,
uhd-images_003.007.001)
i got error when running "uhd_usrp_probe" it fails at checking PPS :
-------
C:\uhd\host\build\utils\Release>uhd_usrp_probe
Win32; Microsoft Visual C++ version 11.0; Boost_105400;
UHD_003.007.000-0-unknown
-- X300 initialization sequence...
-- Determining maximum frame size... 1472 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- Detecting internal GPSDO.... No GPSDO found
-- Initialize Radio control...
-- Creating WSA UDP transport for 192.168.10.2:49153
-- Performing register loopback test... pass
-- Sync DAC's.
-- Creating WSA UDP transport for 192.168.10.2:49153
-- Performing register loopback test... pass
-- Sync DAC's.
-- Initializing clock and PPS references...
Error: RuntimeError: The internal PPS was not detected. Please check
the PPS so
urce and try again.
-----------
when loading the same file-image(usrp_x300_fpga_HGS.bin) but from an
earlier release (24 Mars,uhd-images_003.007.000-48-ge1c32905)
it works OK ,
what have changed ?
-----
C:\uhd\host\build\utils\Release>uhd_usrp_probe
Win32; Microsoft Visual C++ version 11.0; Boost_105400;
UHD_003.007.000-0-unknown
-- X300 initialization sequence...
-- Determining maximum frame size... 1472 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- Detecting internal GPSDO.... No GPSDO found
-- Initialize Radio control...
-- Creating WSA UDP transport for 192.168.10.2:49153
-- Performing register loopback test... pass
-- Sync DAC's.
-- Creating WSA UDP transport for 192.168.10.2:49153
-- Performing register loopback test... pass
-- Sync DAC's.
-- Initializing clock and PPS references...
-- References initialized to internal sources
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X300
| | revision: 4
| | product: 30518
| | mac-addr0: 00:80:2f:0a:ea:62
| | mac-addr1: 00:80:2f:0a:ea:63
| | gateway: 192.168.10.1
| | ip-addr0: 192.168.10.2
| | subnet0: 255.255.255.0
| | ip-addr1: 192.168.20.2
| | subnet1: 255.255.255.0
| | ip-addr2: 192.168.30.2
| | subnet2: 255.255.255.0
| | ip-addr3: 192.168.40.2
| | subnet3: 255.255.255.0
| | serial: F4D29F
| | FW Version: 3.0
| | FPGA Version: 4.0
.........
Regards
Ole Robert Nordli
------------------------------
Message: 2
Date: Fri, 25 Apr 2014 10:06:14 -0700
From: Michael West via USRP-users <[email protected]>
To: ORN <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] X300 ,internal PPS was not detected ?
Message-ID:
<cam4xkrphbogzvez8+zyjjwevwph1xme-2x66n3x4ubwjrgh...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hi Ole,
You are using a newer FPGA image (3.7.1) with older UHD software (3.7.0)
and may be running into a compatibility issue. I would recommend updating
UHD and the FPGA image.
Regards,
Michael E. West
Senior Software Design Engineer
Ettus Research
www.ettus.com
On Fri, Apr 25, 2014 at 9:36 AM, ORN via USRP-users <
[email protected]> wrote:
> Hi
>
> with the latest image "usrp_x300_fpga_HGS.bin" (from 21 april ,
> uhd-images_003.007.001)
> i got error when running "uhd_usrp_probe" it fails at checking PPS :
>
> -------
> C:\uhd\host\build\utils\Release>uhd_usrp_probe
> Win32; Microsoft Visual C++ version 11.0; Boost_105400;
> UHD_003.007.000-0-unknown
>
> -- X300 initialization sequence...
> -- Determining maximum frame size... 1472 bytes.
> -- Setup basic communication...
> -- Loading values from EEPROM...
> -- Setup RF frontend clocking...
> -- Radio 1x clock:200
> -- Detecting internal GPSDO.... No GPSDO found
> -- Initialize Radio control...
> -- Creating WSA UDP transport for 192.168.10.2:49153
> -- Performing register loopback test... pass
> -- Sync DAC's.
> -- Creating WSA UDP transport for 192.168.10.2:49153
> -- Performing register loopback test... pass
> -- Sync DAC's.
> -- Initializing clock and PPS references...
> Error: RuntimeError: The internal PPS was not detected. Please check the
> PPS so
> urce and try again.
> -----------
>
> when loading the same file-image(usrp_x300_fpga_HGS.bin) but from an
> earlier release (24 Mars,uhd-images_003.007.000-48-ge1c32905)
> it works OK ,
> what have changed ?
>
> -----
> C:\uhd\host\build\utils\Release>uhd_usrp_probe
> Win32; Microsoft Visual C++ version 11.0; Boost_105400;
> UHD_003.007.000-0-unknown
>
> -- X300 initialization sequence...
> -- Determining maximum frame size... 1472 bytes.
> -- Setup basic communication...
> -- Loading values from EEPROM...
> -- Setup RF frontend clocking...
> -- Radio 1x clock:200
> -- Detecting internal GPSDO.... No GPSDO found
> -- Initialize Radio control...
> -- Creating WSA UDP transport for 192.168.10.2:49153
> -- Performing register loopback test... pass
> -- Sync DAC's.
> -- Creating WSA UDP transport for 192.168.10.2:49153
> -- Performing register loopback test... pass
> -- Sync DAC's.
> -- Initializing clock and PPS references...
> -- References initialized to internal sources
> _____________________________________________________
> /
> | Device: X-Series Device
> | _____________________________________________________
> | /
> | | Mboard: X300
> | | revision: 4
> | | product: 30518
> | | mac-addr0: 00:80:2f:0a:ea:62
> | | mac-addr1: 00:80:2f:0a:ea:63
> | | gateway: 192.168.10.1
> | | ip-addr0: 192.168.10.2
> | | subnet0: 255.255.255.0
> | | ip-addr1: 192.168.20.2
> | | subnet1: 255.255.255.0
> | | ip-addr2: 192.168.30.2
> | | subnet2: 255.255.255.0
> | | ip-addr3: 192.168.40.2
> | | subnet3: 255.255.255.0
> | | serial: F4D29F
> | | FW Version: 3.0
> | | FPGA Version: 4.0
> .........
>
> Regards
> Ole Robert Nordli
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
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