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Today's Topics:
1. Re: Could this be Ettus X310 self jamming problem?
(=?gb18030?B?VHJlaw==?=)
2. Re: Could this be Ettus X310 self jamming problem?
(Sylvain Munaut)
3. Re: Could this be Ettus X310 self jamming problem?
(=?ISO-8859-1?B?VHJlaw==?=)
4. Re: B200 RX Additional Functionality Questions (Derek Murphy)
5. Re: B200 RX Additional Functionality Questions (Marcus M?ller)
6. Gen3 FPGA Code License? (Tom Wallace)
7. Re: Trouble on loopback for square waves (Neel Pandeya)
----------------------------------------------------------------------
Message: 1
Date: Mon, 6 Apr 2015 00:06:13 +0800
From: "=?gb18030?B?VHJlaw==?=" <[email protected]>
To: "=?gb18030?B?TWFyY3VzIE2ouWxsZXIgdmlhIFVTUlAtdXNlcnM=?="
<[email protected]>,
"=?gb18030?B?TWFyY3VzIE2ouWxsZXIgdmlhIFVTUlAtdXNlcnM=?="
<[email protected]>
Subject: Re: [USRP-users] Could this be Ettus X310 self jamming
problem?
Message-ID: <[email protected]>
Content-Type: text/plain; charset="gb18030"
thanks, is there a formula to calculate all the possible master clock rate?
thanks,
------------------ Original ------------------
From: "Marcus M?ller via USRP-users";<[email protected]>;
Date: Apr 3, 2015
To: "usrp-users"<[email protected]>;
Subject: Re: [USRP-users] Could this be Ettus X310 self jamming problem?
If that solves your problem: 184.32MHz is the third legal
master clock rate.
On 04/02/2015 11:44 PM, Trek via USRP-users wrote:
cool, setting this to 120MHz indeed solved my problem at
1600MHz, however it created another clock harmonic at 1560MHz
(1560=120*13), which is also my point of interest on the spectrum, is
there another odd clock frequency you guys could recommend for me to
work with?
thanks,
------------------ Original ------------------
From: "Marcus M?ller via
USRP-users";<[email protected]>;
Date: Apr 3, 2015
To: "Trek"<[email protected]>;
Cc: ""Marcus M?ller via
USRP-users"<[email protected]>; ""Marcus M?ller via
USRP-users"<[email protected]>;
Subject: Re: Could this be Ettus X310 self jamming
problem?
Try adding "master_clock_rate=120e6" (including quotes) to the
Device Arguments field in the UHD Sink. -Ian
On Apr 2, 2015, at 2:13 PM, Trek <[email protected]>
wrote:
In terms of GRC, how could I adjust
master_clock_rate to 120MHz? Is there a setting in the USRP
source properties?
thanks,
------------------ Original
------------------
From: "Marcus M?ller via
USRP-users";<[email protected]>;
Date: Apr 3, 2015
To: "Martin Braun"<[email protected]>;
Cc: "usrp-users"<[email protected]>;
Subject: Re: [USRP-users]??? Could this
be Ettus X310 self jamming problem?
Try repeating your test with a master_clock_rate of
120MHz rather than 200MHz. This should change the
frequencies of harmonics related to the default radio clock.
-Ian
On Apr 2, 2015, at 1:42 PM, Martin Braun via USRP-users
<[email protected]> wrote:
> On 02.04.2015 07:16, Trek via USRP-users wrote:
>> I already did it at 1.602GHz instead of 1.6GHz,
same thing except now
>> the large spike is -2MHz from 0.
>
> This could be a clock harmonic. At 1650 MHz, do you
still see something?
>
> M
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
>
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 2
Date: Sun, 5 Apr 2015 18:28:42 +0200
From: Sylvain Munaut <[email protected]>
To: Trek <[email protected]>
Cc: Marcus M?ller via USRP-users <[email protected]>
Subject: Re: [USRP-users] Could this be Ettus X310 self jamming
problem?
Message-ID:
<CAHL+j0-BY9-EU+0P+4Q1WnU3b=5rkzi6x5wcswrygl7zghd...@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Hi,
> thanks, is there a formula to calculate all the possible master clock rate?
120M, 184.32M, 200M
That's it. The supported frequencies are hardcoded in UHD.
Cheers,
Sylvain Munaut
------------------------------
Message: 3
Date: Mon, 6 Apr 2015 02:02:42 +0800
From: "=?ISO-8859-1?B?VHJlaw==?=" <[email protected]>
To: "=?ISO-8859-1?B?U3lsdmFpbiBNdW5hdXQ=?=" <[email protected]>
Cc: Marcus M?ller via USRP-users <[email protected]>
Subject: Re: [USRP-users] Could this be Ettus X310 self jamming
problem?
Message-ID: <[email protected]>
Content-Type: text/plain; charset="iso-8859-1"
thanks,
------------------ Original ------------------
From: "Sylvain Munaut";<[email protected]>;
Date: Apr 6, 2015
To: "Trek"<[email protected]>;
Cc: "Marcus M?ller via USRP-users"<[email protected]>; "Marcus M?ller
via USRP-users"<[email protected]>;
Subject: Re: [USRP-users] Could this be Ettus X310 self jamming problem?
Hi,
> thanks, is there a formula to calculate all the possible master clock rate?
120M, 184.32M, 200M
That's it. The supported frequencies are hardcoded in UHD.
Cheers,
Sylvain Munaut
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Message: 4
Date: Sun, 5 Apr 2015 16:59:07 -0400
From: Derek Murphy <[email protected]>
To: Ian Buckley <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] B200 RX Additional Functionality Questions
Message-ID:
<CAPM65Yi9+fzGNdqT9GB3OJHJ6a+tT5Zeqh-e5h_CjMwx8PSO=a...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Ian, again thanks for the great information. I'm sure I'm not the first the
have this problem, do you think there is a possibility of getting this as
an option for a normal fpga flash. That way anybody wanting to do this will
just have to load the firmware and then they could use the UHD to select eh
center LO and then specifically select the other 2 signals.
I might be the only one interested in that but I thought that someone else
might be.
On Sat, Apr 4, 2015 at 5:52 PM, Ian Buckley <[email protected]> wrote:
> B200 uses AD9364 not AD9361?essentially they are identical in programming
> and performance but with only one radio channel.
> The reason I raise the 30.72MHz limit for running in 2 channel mode is
> that these radios only have a single LO (each) for RX and TX.
> So if you want to capture 2 narrow band signals separated by 45MHz you'll
> need to run in single channel mode regardless of which radio version is on
> your USRP because you'll need to center your LO roughly between your 2
> signals so they both fall within the complex sampling bandwidth.
>
>
> On Apr 4, 2015, at 12:32 PM, Derek Murphy <[email protected]> wrote:
>
> Thanks, that's great information. My millage right now on uhd and verilog
> is very low. I will start to look into it.
>
> I thought that since the ad9361 was the same then maybe the firmware could
> be modified to use both the a:rx2 and a:tx/rx could be used at the same
> time. The 30MHz limit is not a big deal because the signal is super narrow.
> On Apr 4, 2015 3:13 PM, "Ian Buckley" <[email protected]> wrote:
>
>> Derek,
>> (You are specifically talking about B200 right? Not B210?)
>> In theory this can be done, but the stock FPGA image won't do it. You
>> would want to use to use the radio in a 1 RX mode because this would allow
>> the use of (upto) a 61.44MHz sample clock between radio and FPGA, rather
>> than the 30.72MHz max when in a 2 RX mode. (B200 doesn't have 2 RX mode
>> anyhow)
>> You would then want to take the B210 FPGA design, strip out the TX DUC's
>> and buffer RAM so that it would fit in the B200's smaller FPGA, and then
>> make one small alteration so that both RX DDC's are fed from the same (1
>> RX) sample bus. (At this point it would look very like the RX design of
>> N210 with 2 RX DDC chains.).
>> From there you have a few details to deal with in UHD (2 DDC's
>> operational, but AD9364 delivering a single RX stream). And finally a flow
>> graph that uses offset LO tuning such that you position the LO at (for
>> example) 22.5MHz between your frequencies of interest and tune the 2
>> CORDICs to +/- 22.5MHz, then decimate both RX streams until they are the
>> right rate to contain your tuned signals of interest but pass freely over
>> USB2.0 bandwidth.
>>
>> It would be at least a days work for me to get that working well I
>> suspect, and I'm very familiar with the FPGA code. Extrapolate your own
>> milage accordingly. You should need very little new code, just a lot of
>> shuffling of existing code, but you'll want a decent understanding of the
>> workings of UHD and some verilog skills.
>>
>> -Ian
>>
>> On Apr 4, 2015, at 7:49 AM, Derek Murphy via USRP-users <
>> [email protected]> wrote:
>>
>> I've done a lot of google research and have not found a solution yet.
>>
>> I wanted to check and see if there is any way to use the B200 in 2 RX
>> mode. I understand that you would not be able to TX at that time and the
>> bandwidth on each RX channel would be lower than the full 56MB.
>>
>> The use case that I am trying to get working in GnuRadio to process two
>> signals that are 45Mhz a part which wouldn't be terrible except the systems
>> that I must use only have USB 2.0. If I could have the B200 use 2 RX each
>> at low bandwidth that seems like it would work, the other option could be
>> to have the B200 set to receive the full span of 45Mhz but filter out the
>> unwanted regions and send back the much smaller result.
>>
>> Thanks
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>>
>>
>
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------------------------------
Message: 5
Date: Sun, 05 Apr 2015 23:05:43 +0200
From: Marcus M?ller <[email protected]>
To: [email protected]
Subject: Re: [USRP-users] B200 RX Additional Functionality Questions
Message-ID: <[email protected]>
Content-Type: text/plain; charset="windows-1252"
Hi Derek,
with the current versions of UHD, you can specify the path to the
firmware and FPGA images you want to use when constructing your device
object, so that's not really the problem here -- the real problem is
that the B200's FPGA size doesn't really allow for a whole second RX
chain without throwing out crucial TX functionality.
Greetings,
Marcus
On 04/05/2015 10:59 PM, Derek Murphy via USRP-users wrote:
> Ian, again thanks for the great information. I'm sure I'm not the
> first the have this problem, do you think there is a possibility of
> getting this as an option for a normal fpga flash. That way anybody
> wanting to do this will just have to load the firmware and then they
> could use the UHD to select eh center LO and then specifically select
> the other 2 signals.
>
> I might be the only one interested in that but I thought that someone
> else might be.
>
> On Sat, Apr 4, 2015 at 5:52 PM, Ian Buckley <[email protected]
> <mailto:[email protected]>> wrote:
>
> B200 uses AD9364 not AD9361?essentially they are identical in
> programming and performance but with only one radio channel.
> The reason I raise the 30.72MHz limit for running in 2 channel
> mode is that these radios only have a single LO (each) for RX and TX.
> So if you want to capture 2 narrow band signals separated by 45MHz
> you'll need to run in single channel mode regardless of which
> radio version is on your USRP because you'll need to center your
> LO roughly between your 2 signals so they both fall within the
> complex sampling bandwidth.
>
>
> On Apr 4, 2015, at 12:32 PM, Derek Murphy <[email protected]
> <mailto:[email protected]>> wrote:
>
>> Thanks, that's great information. My millage right now on uhd and
>> verilog is very low. I will start to look into it.
>>
>> I thought that since the ad9361 was the same then maybe the
>> firmware could be modified to use both the a:rx2 and a:tx/rx
>> could be used at the same time. The 30MHz limit is not a big deal
>> because the signal is super narrow.
>>
>> On Apr 4, 2015 3:13 PM, "Ian Buckley" <[email protected]
>> <mailto:[email protected]>> wrote:
>>
>> Derek,
>> (You are specifically talking about B200 right? Not B210?)
>> In theory this can be done, but the stock FPGA image won't do
>> it. You would want to use to use the radio in a 1 RX mode
>> because this would allow the use of (upto) a 61.44MHz sample
>> clock between radio and FPGA, rather than the 30.72MHz max
>> when in a 2 RX mode. (B200 doesn't have 2 RX mode anyhow)
>> You would then want to take the B210 FPGA design, strip out
>> the TX DUC's and buffer RAM so that it would fit in the
>> B200's smaller FPGA, and then make one small alteration so
>> that both RX DDC's are fed from the same (1 RX) sample bus.
>> (At this point it would look very like the RX design of N210
>> with 2 RX DDC chains.).
>> From there you have a few details to deal with in UHD (2
>> DDC's operational, but AD9364 delivering a single RX stream).
>> And finally a flow graph that uses offset LO tuning such that
>> you position the LO at (for example) 22.5MHz between your
>> frequencies of interest and tune the 2 CORDICs to +/-
>> 22.5MHz, then decimate both RX streams until they are the
>> right rate to contain your tuned signals of interest but pass
>> freely over USB2.0 bandwidth.
>>
>> It would be at least a days work for me to get that working
>> well I suspect, and I'm very familiar with the FPGA code.
>> Extrapolate your own milage accordingly. You should need very
>> little new code, just a lot of shuffling of existing code,
>> but you'll want a decent understanding of the workings of UHD
>> and some verilog skills.
>>
>> -Ian
>>
>> On Apr 4, 2015, at 7:49 AM, Derek Murphy via USRP-users
>> <[email protected]
>> <mailto:[email protected]>> wrote:
>>
>>> I've done a lot of google research and have not found a
>>> solution yet.
>>>
>>> I wanted to check and see if there is any way to use the
>>> B200 in 2 RX mode. I understand that you would not be able
>>> to TX at that time and the bandwidth on each RX channel
>>> would be lower than the full 56MB.
>>>
>>> The use case that I am trying to get working in GnuRadio to
>>> process two signals that are 45Mhz a part which wouldn't be
>>> terrible except the systems that I must use only have USB
>>> 2.0. If I could have the B200 use 2 RX each at low bandwidth
>>> that seems like it would work, the other option could be to
>>> have the B200 set to receive the full span of 45Mhz but
>>> filter out the unwanted regions and send back the much
>>> smaller result.
>>>
>>> Thanks
>>> _______________________________________________
>>> USRP-users mailing list
>>> [email protected] <mailto:[email protected]>
>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>
>
>
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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Message: 6
Date: Mon, 6 Apr 2015 14:29:00 +0000
From: Tom Wallace <[email protected]>
To: "[email protected]" <[email protected]>
Subject: [USRP-users] Gen3 FPGA Code License?
Message-ID:
<c69bc2a4e2e45749a232e19ea6c5255d1abed...@ex10dag10-n1.apps4rent.net>
Content-Type: text/plain; charset="us-ascii"
>From the Git repo logs, it looks like the Gen3 FPGA code had the GPLv3 license
>statements removed last year. Is there a license that describes the terms
>under which the Gen3 code is now distributed?
In particular, is it still distributed under an open source license, and if so,
what flavor (BSD/GPL/LGPL/other)?
---
Tom Wallace ([email protected]<mailto:[email protected]>)
Vesperix Corporation
803 West Broad Street, Suite 520
Falls Church, VA 22046
Phone 703-224-4422 Mobile 703-220-8711
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Message: 7
Date: Mon, 6 Apr 2015 08:55:23 -0700
From: Neel Pandeya <[email protected]>
To: Soumen Banerjee <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Trouble on loopback for square waves
Message-ID:
<CACaXmv8J8AsTih2ke-7yt6GZKa5cH2D7hV=eae-ms83b2wl...@mail.gmail.com>
Content-Type: text/plain; charset="utf-8"
Hello Soumen:
At first glance, I don't immediately see any problem with your code. It
might be helpful to look at the "tx_waveforms" utility in the
"uhd/host/examples" folder. It also generates square waves.
Which USRP and which daughterboard are you using? What sample rate?
--Neel
On 1 April 2015 at 04:52, Soumen Banerjee via USRP-users <
[email protected]> wrote:
> Hi,
>
> I am having some trouble sending and receiving square waves using uhd
> programs. I have the receiver and transmitter connected using rf cable. On
> the exact same program, I am able to send and receive sine waves properly
> though. I have attached the code I'm using to transmit and receive the data
> into the file. All the parameters are hardcoded in the code file itself.
>
> Simply exchanging line 230 with line 231 causes it to work just fine(for
> sine waves).
>
> Also attached is a snapshot of what I get instead of square waves.
>
> Can someone please help? Im totally stuck on this one!
>
> Regards,
> Soumen
>
> _______________________________________________
> USRP-users mailing list
> [email protected]
> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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