Hi all, I have this error when trying to simulate a custom RFNoC block in an OOT module:
$ make noc_block_hbFilter_tb ..... ..... Starting static elaboration ERROR: [VRFC 10-2063] Module <fir_compiler_0> not found while processing module instance <fir_compile_0_inst> [/home/tienvh/workspace/rfnoc/src/rfnoc-filters/rfnoc/fpga-src/noc_block_hbFilter.v:179] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-99] Step results log file:'/home/tienvh/workspace/rfnoc/src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/home/tienvh/workspace/rfnoc/src/rfnoc-filters/rfnoc/testbenches/noc_block_hbFilter_tb/xsim_proj/xsim_proj.sim/sim_1/behav/elaborate.log' file for more information. ..... ..... I can build an FPGA image with the custom RFNoC block following the instruction here: http://www.synchronouslabs.com/blog/creating-a-custom-rfnoc-block-with-using-xillinx-ip but I haven't found a way to simulate this block. Is there any way to run the simulation in this situation? Otherwise it would be difficult to debug if anything goes wrong.. Thanks in advance. Best, Tien
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