Hi everyone,
I am currently working with the X310 and two TwinRX daugerboards and have a problem understanding the processing done in the FPGA. As far as I understood the TwinRX works as a super-het and has the second (ADC) IF at 150 MHz with 80 MHz bandwidth (according to the block diagram in the schematics). The ADC of the X310 runs at 200 Msps, so it is working with undersampling I guess? Now I am missing a block diagram of what is happening in the FPGA. My guess is that he will mix the ADC signal with a complex sine-wave so that the 150 MHz will be at zero -> exp(-j*2*pi*150MHz*t). After that there has to be some sort of filtering and downsampling. But which exactly? According to the warning message I get depending on the sample rate I set, I guess there are multiple half-band filters and an CIC filter which are used in different combinations to get the required sample rate. Is there somewhere a block diagram and rules for that? Now to my main problem: I get a lot of aliasing. For example I have set my sample rate to 10e6, I can tune my generator several times the bandwidth above the center frequency and will still see it with barely any atenuation. Additionally I noticed setting the RX bandwidth has no effect. Even if I set it to a very low value (100kHz) at 10Msps, I see no effect. Do I have to implement the digital filters my own using RFNoC? What is the set_rx_bandwidth() function good for? I know there are board which do not support this function but as far as I understood then the board will report the currently used bandwidth when calling get_rx_bandwidth() - mine always reports the value I set.
Best regards, Fabian _______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
