On 03/07/2018 08:07 PM, liu Jong via USRP-users wrote:
Hi all,
Do you give us some advice?
thank you.
best regards
Jon
This is pretty-much what electronics *DOES*.
There will be harmonics of the master clock at some level, and only 5dB
above the noise is actually really good.
Unless each compartment of a modern radio is in its own EMI-isolated
package, there will be some radiation of clock signals.
It's inevitable, so, you choose your master clock to not coincide
with any of desired signal frequencies, wherever possible, and if
not you have a "map" of frequencies that are likely to contain
low-level harmonics of clocks inside the electronics.
ANY wide-band modern receiver has this problem. But for many
single-purpose applications, clock choices are made to avoid it
being a problem or, if the harmonics are low (like only +5dB above
the noise), simply ignored.
2018-03-06 11:48 GMT+08:00 liu Jong <jongliu1...@gmail.com
<mailto:jongliu1...@gmail.com>>:
Hi all,
We test it with matlan2017b.But we don't think it does with softwere.
best regards
Jon
2018-03-05 10:29 GMT+08:00 liu Jong <jongliu1...@gmail.com
<mailto:jongliu1...@gmail.com>>:
Hi all,
Any suggestion is welcome.
2018-03-02 14:21 GMT+08:00 liu Jong <jongliu1...@gmail.com
<mailto:jongliu1...@gmail.com>>:
Hi all,
When we set "master_clock_rate=25.6M" for Receiving
and we found that there is a Single frequency interference
in 76.8M(25.6X3),102.4M(25.6X4),153.6M and so on until
above 1.5G.We changed the "master_clock_rate=16M",and we
also found that there is a Single frequency interference
in 80M(16X5),96M(16X6)and so on.The signal power is
larger than noise about 5db.Is it the problem of the chip
or the problem of USRP E310?
thank you
best regards
Jon
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