Am I able to run make in Windows using Cygwin for ISE 14.7? I tried to run make 
PROJECT_ONLY=1 , and this is what I get.

/bin/sh: xtclsh: command not found
ISE Version:
make -f proj NAME=B200 DEVICE=XC6SLX75 EXTRA_DEFS=" "
make[1]: Entering directory 
/bin/sh: xtclsh: command not found
/bin/sh: xtclsh: command not found
1d7/usrp3/top/tcl/ise_helper.tcl ""
/bin/sh: xtclsh: command not found
make[1]: *** [../Makefile.common:52: build-B200//b200.xise] Error 127
make[1]: Leaving directory 
make: *** [Makefile:73: B200] Error 2


I ran source C:/Xilinx/14.7/ISE_DS/settings64.bat and I got this

$ source C:/Xilinx/14.7/ISE_DS/settings64.bat
-bash: @echo: command not found
-bash: C:/Xilinx/14.7/ISE_DS/settings64.bat: line 2: syntax error near 
unexpected token `('
-bash: C:/Xilinx/14.7/ISE_DS/settings64.bat: line 2: `REM Copyright (c) 
1995-201' Xilinx, Inc.  All rights reserved.

From: Robin Coxe []
Sent: Monday, 9 April 2018 11:16 AM
To: Yeo Jin Kuang Alvin (IA)
Subject: Re: [USRP-users] Ettus Code (FPGA) for USRP B210

B200.v is the top level Verilog file.  If you inspect this file, you will see 
that B200_core.v and B200_io.v are instantiated within it.

All of our FPGA code is freely available-- please take some time to look 
through the files in the usrp3/lib directories here:


On Mon, Apr 9, 2018 at 10:59 AM, Yeo Jin Kuang Alvin (IA) via USRP-users 
<<>> wrote:
Hi everyone,

I want to use the ettus code for the USRP B210, however, may I know which is 
the Top file as I noticed there are 3 different ones. B200.v , B200_core.v , 
B200_io.v. Tried to add the source file to Xilinx ISE 14.7 but there are some 
files that I couldn’t find, eg. Gpif_sync, slave_fifo32, uart_timing_fifo etc.

What are the essentials file and where do I find it?

Thanks in advance!

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