On 04/15/2018 06:20 PM, Miklos Maroti via USRP-users wrote: > Dear All, > > I am new to RFNoC development, and hope some of you can give some > insight. I was looking the fpga-src repository, and reading RFNoC docs > online. Reading the source code I see that m_axis_data_tdata and > s_axis_data_tdata are always 32 bit wide (16+16 bits for I/Q). I would > like to process two streams on an X310 coming from two UB160 > daughter-boards in sync at 100 MHz sampling rate. Can I just connect > two noc_block_ddc's to a single custom RFNoC processing engine with > two input and two output ports? Then how do I hook this up to the PC > in a way that if there are lost packets in either direction, then on > both channels I loose the same amount of samples?
Yes, you can connect two DDC outputs to two inputs of your custom block. Then connect your custom block to a host-side streamer. Depending on your implementation, you don't loose any samples. -- M _______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
