Hello Peter, Yes, that is correct, you need multiple AXI wrappers and (optionally) multiple header encoders if you are dealing with multiple ports. From the blocks from our codebase, the DDC [1] and DUC [2] have multiple port configuration, which is done on a for loop, but they don't have header modifiers unlike the DmA FIFO [3] which includes that for multiple ports.
You can clearly set each port manually, without a for loop, depending if each port is dedicated to a different operation. Regards, - Nicolas [1] https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/noc_block_ddc.v [2] https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/noc_block_duc.v [3] https://github.com/EttusResearch/fpga/blob/rfnoc-devel/usrp3/lib/rfnoc/noc_block_axi_dma_fifo.v On Wed, May 16, 2018 at 4:05 PM, Peter Horvath via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello, > > I'm trying to hack together an RFNoC source block with two outputs, รก la > siggen but with more outputs obviously. Is it correct that I need two AXI > wrappers and two cvita_hdr_encoders, and I need to multiplex the outputs of > the AXI wrappers? If this is acceptable, what is the best way to implement > this multiplexing? Is there an existing block that I could use as a > reference? > Best regards, > Peter > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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