I'm not an FPGA expert by a long shot so I'm afraid I can't point at anything specific. The DRAM FIFO may offer some inspiration or the SRAM FIFOs. How and where you need to access the data will influence what the best solution is. Can you say anything more about your application? That would likely help other, more experienced, people on the list to give you more specific advice.
Derek On Fri, Jun 8, 2018 at 12:06 PM, shachar J. brown <[email protected]> wrote: > Thank you Jonathon and Derek, > > Derek, you are absolutely correct. I'm not planning on storing filter taps > but rather generic data, and lots of it. Likewise, I'm planning on changing > the data on the run. What's your suggestion for the most efficient way on > doing this? (By efficient, I mean a way that doesn't clog the 128 available > registers). > > Thanks again, > Steve > > On Fri, Jun 8, 2018 at 9:57 AM, Derek Kozel <[email protected]> wrote: > >> Hi Steve, >> >> As an addon to Jonathon's email, you haven't actually said that you want >> to store filter taps. If you are storing generic data then the embedded >> regs are unlikely to be helpful for you because you are not going to be >> using the data with DSP48s. >> >> Regards, >> Derek >> >> On Fri, Jun 8, 2018 at 6:04 AM, Jon Pendlum via USRP-users < >> [email protected]> wrote: >> >>> Hi Steve, >>> >>> USE_EMBEDDED_REGS_COEFFS means that the filter will attempt to infer >>> the DSP48's embedded registers (specifically register B) for storing >>> coefficients. You should refer to Xilinx's DSP48 design doc >>> https://www.xilinx.com/support/documentation/user_guides/ug4 >>> 79_7Series_DSP48E1.pdf. >>> >>> Using embedded registers is more efficient, because those registers >>> come for free as part of the DSP48. However, the embedded registers >>> only have a reset and will initialize to all 0s (instead of the >>> coefficients in COEFFS_VEC). At startup, the coefficients must be >>> loaded via the settings register bus for the filter to be useful. This >>> is not a big deal though, since the block controller for >>> noc_block_fir_filter does that. Also, since the embedded registers are >>> chained like shift register (via BCOUT output to B input), loading new >>> coefficients while streaming causes the FIR filter output to be >>> corrupted until all the new coefficients have been loaded. >>> >>> If you set USE_EMBEDDED_REGS_COEFFS = 0, then regular registers will >>> be instantiated. Those registers will be initialized with COEFFS_VEC >>> and the filter will always be ready to go. Also, the output will not >>> be corrupted while loading new coefficients. >>> >>> I would suggest enabling USE_EMBEDDED_REGS_COEFFS unless you plan to >>> constantly change coefficients and are worried about the filter output >>> being corrupted. >>> >>> Jonathon >>> >>> On Fri, Jun 8, 2018 at 12:06 AM, shachar J. brown via USRP-users >>> <[email protected]> wrote: >>> > After examining the files in depth, I realized I need some help >>> > understanding core concepts in FPGA programming: >>> > >>> > In "axi_fir_filter.v" there is a parameter named >>> "USE_EMBEDDED_REGS_COEFFS", >>> > and explained in comment: " Reduce register usage by only using >>> embedded >>> > registers in DSP slices". >>> > >>> > - What is the actual difference between registers and embedded >>> registers? >>> > - Does the implementation of the two only differ in usage of "wire" vs. >>> > "reg"? >>> > >>> > Thanks for your time, >>> > Steve >>> > >>> > On Thu, Jun 7, 2018 at 11:28 AM, Nick Foster <[email protected]> >>> wrote: >>> >> >>> >> It's going to depend on how much block RAM the image is already >>> using, and >>> >> how much more you can use while still getting the image to route. The >>> >> easiest way to find out will be to try it. >>> >> >>> >> On Thu, Jun 7, 2018, 9:14 AM shachar J. brown < >>> [email protected]> >>> >> wrote: >>> >>> >>> >>> Thanks Nick, that's an excellent example. >>> >>> Do you know what are the memory size restrictions of the >>> configuration >>> >>> data? >>> >>> >>> >>> On Thu, Jun 7, 2018 at 10:50 AM, Nick Foster <[email protected]> >>> >>> wrote: >>> >>>> >>> >>>> Look at the RFNoC FIR filter block for a good example of pushing >>> >>>> configuration data into a block via the settings bus. >>> >>>> >>> >>>> On Thu, Jun 7, 2018, 8:25 AM shachar J. brown via USRP-users >>> >>>> <[email protected]> wrote: >>> >>>>> >>> >>>>> Hi all, >>> >>>>> >>> >>>>> I'm working on an X310. >>> >>>>> >>> >>>>> I have large data (tables of 1-3 K of variables) I would like to >>> insert >>> >>>>> into the FPGA's memory registers while running. >>> >>>>> >>> >>>>> How much space is available in the FPGA? Seemingly, the Address >>> for the >>> >>>>> "set_register" is only 8 bits long, and the first 128 addresses >>> are reserved >>> >>>>> for the Noc_Shell. So... Does that mean I can store only 128 >>> variables at a >>> >>>>> time? >>> >>>>> >>> >>>>> (Just to clarify: I want to change the data while running, and I'd >>> like >>> >>>>> it to be inside the FPGA for performance issues). >>> >>>>> >>> >>>>> Thank a ton! >>> >>>>> Steve >>> >>>>> _______________________________________________ >>> >>>>> USRP-users mailing list >>> >>>>> [email protected] >>> >>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >>> >>> >>> > >>> > >>> > _______________________________________________ >>> > USRP-users mailing list >>> > [email protected] >>> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> > >>> >>> _______________________________________________ >>> USRP-users mailing list >>> [email protected] >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >> >> >
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