Hi Nick, This sounds like there may still be a bug in the new DDC/DUC's since the change from CORDIC to DDSes [0]. There was a similar issue [1][2] but the patch was merged in at 3.14.0.0 [3].
Could you try a UHD version pre-3.12.0.0 to see if it resolves the issue? 3.11.1.0 or 3.10.3.0 would be my recommendation. [0] - https://github.com/EttusResearch/uhd/blob/master/CHANGELOG#L365 [1] - https://github.com/EttusResearch/uhd/issues/211 [2] - https://github.com/EttusResearch/fpga/pull/35 [3] - https://github.com/EttusResearch/fpga/commit/fdd77081c4aaa2c79d56eb08516bdb563f9b6a89 Regards, Nate Temple On Sat, Jun 15, 2019 at 11:08 AM Nick Foster via USRP-users < [email protected]> wrote: > Yes to both!. That's what led me to believe the rate was wrong. LFRX is DC > coupled, but the arrangement it's in has the next component in the chain > blocking DC. > > I tested with gr-ettus/device3 today, and the bug isn't there. So I think > there's something in the legacy driver. > > Nick > > On Sat, Jun 15, 2019 at 11:03 AM Ian Buckley <[email protected]> > wrote: > >> Go tune WWV, your friendly Federal signal generator? >> (Also isn’t LFRX DC coupled?) >> >> > On Jun 14, 2019, at 11:43 PM, Nick Foster via USRP-users < >> [email protected]> wrote: >> > >> > Got a weird one here. I'm using an X310 with UHD 3.14.0.0-87-g4e084337, >> with two LFRX daughterboards installed. Legacy interface with gr-uhd, not >> gr-ettus, just testing things in the field. When I tune to 15MHz sample >> rate at 1Msps, I get a resulting stream that looks for all the world like >> it's coming in at 7.5MHz and 500ksps. Because this is a field deployment, >> and because I don't have immediate access to a signal generator, it's a bit >> hard to confirm that. It looks to me (at first blush) like the DDC block is >> getting an incorrect master clock rate, and setting its tick rate >> accordingly. When I set the frequency to 30MHz and the sample rate to >> 2Msps, I get the result I'm expecting. >> > >> > I don't believe I'm seeing the same problem with device3/gr-ettus, but >> I'll test that further today. Anyone seen behavior like this before? >> There's also an unexpected DC offset I haven't seen before, if that helps >> jog anyone's memory. Since it's direct-sampled, not zero-IF, any DC offset >> must be the result of the DSP chain. >> > >> > Nick >> > _______________________________________________ >> > USRP-users mailing list >> > [email protected] >> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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