We think we are using both cards. This is my uhd_usrp_probe:
[INFO] [UHD] linux; GNU C++ version 7.4.0; Boost_106501;
UHD_3.14.1.1-release
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Connecting to niusrpriorpc at localhost:5444...
[INFO] [X300] Using LVBITX bitfile
/usr/share/uhd/images/usrp_x310_fpga_HG.lvbitx...
[INFO] [X300] Radio 1x clock: 200 MHz
[INFO] [GPS] No GPSDO found
[INFO] [0/DmaFIFO_0] Initializing block control (NOC ID: 0xF1F0D00000000000)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1319 MB/s)
[INFO] [0/DmaFIFO_0] BIST passed (Throughput: 1292 MB/s)
[INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD100000000001)
[INFO] [0/Radio_1] Initializing block control (NOC ID: 0x12AD100000000001)
[INFO] [0/DDC_0] Initializing block control (NOC ID: 0xDDC0000000000000)
[INFO] [0/DDC_1] Initializing block control (NOC ID: 0xDDC0000000000000)
[INFO] [0/DUC_0] Initializing block control (NOC ID: 0xD0C0000000000000)
[INFO] [0/DUC_1] Initializing block control (NOC ID: 0xD0C0000000000000)
[WARNING] [X300] Cannot update master clock rate! X300 Series does not
allow changing the clock rate during runtime.
_____________________________________________________
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X310
| | revision: 11
| | revision_compat: 7
| | product: 30959
| | mac-addr0: 00:80:2f:24:16:c9
| | mac-addr1: 00:80:2f:24:16:ca
| | gateway: 192.168.10.1
| | ip-addr0: 192.168.10.2
| | subnet0: 255.255.255.0
| | ip-addr1: 192.168.20.2
| | subnet1: 255.255.255.0
| | ip-addr2: 192.168.30.2
| | subnet2: 255.255.255.0
| | ip-addr3: 192.168.40.2
| | subnet3: 255.255.255.0
| | serial: 3179406
| | FW Version: 6.0
| | FPGA Version: 35.1
| | FPGA git hash: bb85bdf
| | RFNoC capable: Yes
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: TwinRX Rev C (0x0095)
| | | Serial: 31793E9
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: TwinRX RX0
| | | | Antennas: RX1, RX2
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | | Connection Type: II
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 1
| | | | Name: TwinRX RX1
| | | | Antennas: RX1, RX2
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | | Connection Type: QQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | RX Dboard: B
| | | ID: TwinRX Rev C (0x0095)
| | | Serial: 31793F0
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: TwinRX RX0
| | | | Antennas: RX1, RX2
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | | Connection Type: II
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 1
| | | | Name: TwinRX RX1
| | | | Antennas: RX1, RX2
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range all: 0.0 to 93.0 step 1.0 dB
| | | | Bandwidth range: 80000000.0 to 80000000.0 step 0.0 Hz
| | | | Connection Type: QQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: B
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: Unknown (0x0094)
| | | Serial: 31793E9
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: Unknown (0x0094) - 0
| | | | Antennas:
| | | | Sensors:
| | | | Freq range: 0.000 to 0.000 MHz
| | | | Gain Elements: None
| | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX Dboard: B
| | | ID: Unknown (0x0094)
| | | Serial: 31793F0
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: Unknown (0x0094) - 0
| | | | Antennas:
| | | | Sensors:
| | | | Freq range: 0.000 to 0.000 MHz
| | | | Gain Elements: None
| | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: B
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | RFNoC blocks on this device:
| | |
| | | * DmaFIFO_0
| | | * Radio_0
| | | * Radio_1
| | | * DDC_0
| | | * DDC_1
| | | * DUC_0
| | | * DUC_1
El 20/10/2019 a las 17:18, Marcus D Leech escribió:
Which daughter cards are you using?
Could you share the output of uhd_usrp_probe on the device?
Sent from my iPhone
On Oct 20, 2019, at 8:40 AM, Pablo Martínez de Leiva Díaz via USRP-users
<[email protected]> wrote:
Hi all,
We have a x310 SDR, we are obtaining IQ samples from 4 channels but we are
having problems with tune frequency.
When we already have set up one frequency, 100Mhz for example, and we try to
tune a frequency very distant from the current, 700mhz for example, we get this
error:
terminate called after throwing an instance of 'uhd::io_error'
what(): EnvironmentError: IOError: Block ctrl (CE_01_Port_40) no response
packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl<_endianness>::wait_for_ack(bool, double) [with
uhd::endianness_t _endianness = (uhd::endianness_t)1; uint64_t = long unsigned int]
at /build/uhd-ynzbn9/uhd-3.14.1.1/host/lib/rfnoc/ctrl_iface.cpp:142
This is the function we use for tuning:
bool sdr_set_tune_frequency(usrp_2945* radio, float freq, int channels) {
bool success = true;
std::cout << "Setting tune frequency: " << freq;
uhd::tune_request_t tune(freq);
for (int i = 0; i < channels; ++i) {
radio->usrp->set_rx_freq(tune, i);
if (std::abs(radio->usrp->get_rx_freq(i) - freq) > 0.0001){ // Here we
check if the change have been done correctly
success = false;
}
}
return success;
}
We have the release version 3.14.1.1 of UHD.
I hope you can help us, thanks beforehand.
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