Hi, looking at the generated code from the uhd_image_builder.py it declares ce_clk and ce_rst and assigns them to radio_clk and radio_rst. Actually this file is included within x300_core.v which already has the same signals as input ports and which are externally connected in x300.v to a different clock (at 214MHz). do I understand correctly that the assignments are ignored and that the signals stay at 214MHz rather than the 200 MHz of the radio_clk? Is there any reason why the builder script adds those declarations/assignments? Thanks,
Dario Pennisi
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