Hi Dario, I suspect this might be a bug. The ce_clk signal is an input in x300_core.v, but it is also assigned to radio_clk. On the other hand, other devices do not have a ce_clk input for their *_core.v implementations. Do you run into any synth errors when building a X300 rfnoc image?
Jonathon On Thu, Oct 31, 2019 at 11:49 PM Dario Pennisi via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > looking at the generated code from the uhd_image_builder.py it declares > ce_clk and ce_rst and assigns them to radio_clk and radio_rst. Actually > this file is included within x300_core.v which already has the same signals > as input ports and which are externally connected in x300.v to a different > clock (at 214MHz). > > do I understand correctly that the assignments are ignored and that the > signals stay at 214MHz rather than the 200 MHz of the radio_clk? > > Is there any reason why the builder script adds those > declarations/assignments? > > Thanks, > > > > Dario Pennisi > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >
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