Hi Ivan,
You should be able to build an FPGA image with 2 FFT blocks and 2 window
blocks.  I have done something similar on the E310 where I have 2 FFT
blocks and then 2 custom blocks which pass/discard selected FFT bins (and
is actually reasonably similar to the window block).  A couple of points:

   - You will want to create your own FFT IP component from the Vivado IP
   builder tool.  The Ettus FFT noc block includes a 4096 point FFT.  In order
   to conserve resources, you could reduce the size, change the option to be
   fixed size (rather than variable size), and change the architecture (from
   pipelined to radix-4 or radix-2).  Each of these will affect overall
   resources and performance.  If you need the FFT to keep up at the full
   radio rate, though, you probably need to stick with 'pipelined'.
   - If your FFT is bigger than 512 points, you will need to set
   RESIZE_OUTPUT_PACKET=1 in the axi_wrapper so that it can change the
   outgoing packet size to match the incoming packet size.  Otherwise, the FFT
   output packets of 1024 points or more will be a problem for the E310.
   - You will likely want to combine the FFT and window functionality into
   1 new noc block.  My original plan of 2 FFTs and 2 custom blocks did not
   build, but when I combined the functionality into a total of 2 blocks (each
   with one FFT and one custom block), it built.  So, perhaps there is a
   non-negligible amount of overhead in having things in separate noc blocks.
   You could even try to combine all of your functionality into a single 2x2
   noc block.
   - Depending on whether or not you need Tx capability, you could
   potentially not include the DUC.  Also, if you plan to run at full radio
   rates such that you won't need a DDC, you could eliminate the DDC from the
   build.

My experience is with 3.13, 3.14, 3.15.  I have not tried any builds with
the new 'master' branch (eventually becoming 4.0).  From what I understand
about the new 'master', you could statically connect your noc blocks such
that you might not need to do my 'trick' of putting multiple noc block
functionality into a single noc block in order to save resources.

Rob


On Sat, Apr 4, 2020 at 2:04 PM Ivan Zahartchuk via USRP-users <
[email protected]> wrote:

> Yes, I really get an error
>  The packing of instances into the device could not be ovailable, however, 
> the unplaced instances require 9681 slices. Please analyze your design to 
> determine if the number of LUTs, FFs, and / or control sets can be reduced.
> ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed 
> please check previous errors for details.'
> beyed. There are a total of 13300 slices in the pblock, of which 8368 slices 
> are available, however, the unplaced instances require 9681 slices. Please 
> analyze your design to determine if the number of LUTs, FFs, and / or control 
> sets can be reduced.
> ERROR: [Place 30-99] Placer failed with error: 'Detail Placement failed 
> please check previous errors for details.
> But do not tell me if there are blocks in gnuradio to control gpio. The 
> general idea is to implement an amplitude or phase direction finder on a 
> given board. Perhaps you have any suggestions or examples. Because in 
> programming on FPGAs I am unfortunately very weak and I need decent speed.
>
>
> сб, 4 апр. 2020 г. в 20:50, Marcus D. Leech via USRP-users <
> [email protected]>:
>
>> On 04/04/2020 01:39 PM, Ivan Zahartchuk via USRP-users wrote:
>>
>>
>> Hello. Can I create a binary file with two fft blocks and two window
>> blocks for usrp E310 for rfnoc? And if so, how ? The idea is to receive a
>> signal from two channels simultaneously.
>>
>>
>> _______________________________________________
>> USRP-users mailing 
>> [email protected]http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>>
>> There may not be enough room for two FFT blocks in the E310 FPGA.  But
>> regardless, you'd need Xylinx Vivado tooling to generate up an RFNOC
>>   FPGA image that has the appropriate blocks generated into it. There is
>> no "dynamic" generation of blocks in the FPGA.  The only "dynamic"
>>   part is the connection of those blocks across the cross-bar construct
>> that RFNoC uses.
>>
>> This document may be helpful:
>>
>> https://kb.ettus.com/Getting_Started_with_RFNoC_Development
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