Is the windows Cygwin build of the E310_SG3 target being maintained?

I have been following the build instructions and have Vivado 2019.1 installed.  
It is failing in multiple points in the generation of the IP.  I had to correct 
some paths that should have been windows-ized but did not seem to be in 
tools/make/viv_hls_ip_builder.mak.

I can build at least one of the components (IP fifo_short_2clk), so I am 
somewhat confident that Vivado is installed correctly, and that my 'source 
setupenv.sh' was done properly.

However now I am getting this error which is just impenetrable (this is with a 
clean git pull, not the changes I reference above):

========================================================
BUILDER: Building IP mig_7series_0 - zynq xc7z020/clg484/-3
========================================================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: 
/cygdrive/c/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/mig_7series_0
BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source 
C:/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl
 -log mig_7series_0.log -nojournal
[00:00:47] Current task: Initialization +++ Current Phase: Starting
[00:00:48] Current task: Initialization +++ Current Phase: Finished
[00:00:48] Process terminated. Status: Failure

========================================================
Warnings:           0
Critical Warnings:  0
Errors:             0

BUILDER: Releasing IP location: 
/cygdrive/c/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/mig_7series_0
make[1]: *** 
[/cygdrive/c/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/top/e31x/ip/mig_7series_0/Makefile.inc:32:
 
/cygdrive/c/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/mig_7series_0/mig_7series_0.xci]
 Error 1
make[1]: Leaving directory 
'/cygdrive/c/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/top/e31x'
make: *** [Makefile:71: E310_SG3] Error 2


build-ip/xc7z020clg484-3/ mig_7series_0.log is not helpful:

#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Mon Apr 20 19:14:06 2020
# Process ID: 181720
# Current directory: 
C:/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3
# Command line: vivado.exe -mode batch -source 
C:/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl
 -log mig_7series_0.log -nojournal
# Log file: 
C:/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/mig_7series_0.log
# Journal file:
#-----------------------------------------------------------
source 
C:/Users/user/Documents/e310/usrp/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl
# set xci_file         $::env(XCI_FILE)               ;
# set part_name        $::env(PART_NAME)              ;
# set gen_example_proj $::env(GEN_EXAMPLE)            ;
# set synth_ip         $::env(SYNTH_IP)               ;
# set ip_name [file rootname [file tail $xci_file]]   ;
# file delete -force "$xci_file.out"
# create_project -part $part_name -in_memory -ip
# set_property target_simulator XSim [current_project]
# add_files -norecurse -force $xci_file
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 
'C:/Xilinx/Vivado/2019.1/data/ip'.


There appears to be an error file and a core file:
$ cat hs_err_pid181720.log
#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.


Is this build maintained enough to use? Because of my limited setup at home, I 
really don't want to spin up a new server or VM for this, but if it is required 
then I guess I will.

Thanks,
Dan Harris

  

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