Hi Snehasish,

The DDC supports a wide range of sampling rates. Depending on the rates you
want, some of the DDC filters could be removed to reduce utilization or
there may be a better architecture to fit your situation. What rates do you
need to support?

Jonathon

On Thu, Apr 23, 2020 at 3:19 AM Snehasish Kar via USRP-users <
usrp-users@lists.ettus.com> wrote:

> Hello Brian
>
> While writing the bitstream it gave an error stung the current design
> didn’t satisfy the timing constraint.
>
> I tried creating 12 blocks of DDC 1 to 2, blocks but that failed too
> saying the placer couldnot place more than 5% of the movable instances in
> the design.
>
> Regards
> Snehasish
>
> Get Outlook for iOS <https://aka.ms/o0ukef>
> ------------------------------
> *From:* Brian Padalino <bpadal...@gmail.com>
> *Sent:* Thursday, April 23, 2020 4:19:14 AM
> *To:* Snehasish Kar <snehasish....@live.com>
> *Cc:* usrp-users@lists.ettus.com <usrp-users@lists.ettus.com>
> *Subject:* Re: [USRP-users] Modifying RFNoC ddc block for 16 parallel
> instances
>
> On Wed, Apr 22, 2020 at 6:17 PM Snehasish Kar <snehasish....@live.com>
> wrote:
>
> Hello Brian
>
> Thanks for your response, actually I tried using DDC 1 to n block as given
> here, but giving 1 to 8 channels have a timing issue, while generating the
> build. So I thought it as an alternative plan.
>
>
> https://gitlab.com/theseus-cores/theseus-cores/-/blob/master/fpga-rfnoc/README.md#dsp-utilsnoc_block_ddc_1_to_n
>
>
> What was the timing issue?  Is it possible for you to break up the logic
> to help relax timing constraints?
>
> Brian
>
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