Hello Jonathon I need to use a sample rate between 20ksps to 1msps.
Btw I tried following Brian's advice about breaking the logic. I was able to use to build a fpga image with 2x1:4 DDC block. Though I required 1:16 DDC block, but still it is great to start working. @Brian Padalino<mailto:bpadal...@gmail.com>: Thanks a lot for the help. Regards ________________________________ From: Jonathon Pendlum <jonathon.pend...@ettus.com> Sent: Friday, April 24, 2020 9:00 AM To: Snehasish Kar <snehasish....@live.com> Cc: Brian Padalino <bpadal...@gmail.com>; usrp-users@lists.ettus.com <usrp-users@lists.ettus.com> Subject: Re: [USRP-users] Modifying RFNoC ddc block for 16 parallel instances Hi Snehasish, The DDC supports a wide range of sampling rates. Depending on the rates you want, some of the DDC filters could be removed to reduce utilization or there may be a better architecture to fit your situation. What rates do you need to support? Jonathon On Thu, Apr 23, 2020 at 3:19 AM Snehasish Kar via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hello Brian While writing the bitstream it gave an error stung the current design didn’t satisfy the timing constraint. I tried creating 12 blocks of DDC 1 to 2, blocks but that failed too saying the placer couldnot place more than 5% of the movable instances in the design. Regards Snehasish Get Outlook for iOS<https://aka.ms/o0ukef> ________________________________ From: Brian Padalino <bpadal...@gmail.com<mailto:bpadal...@gmail.com>> Sent: Thursday, April 23, 2020 4:19:14 AM To: Snehasish Kar <snehasish....@live.com<mailto:snehasish....@live.com>> Cc: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> Subject: Re: [USRP-users] Modifying RFNoC ddc block for 16 parallel instances On Wed, Apr 22, 2020 at 6:17 PM Snehasish Kar <snehasish....@live.com<mailto:snehasish....@live.com>> wrote: Hello Brian Thanks for your response, actually I tried using DDC 1 to n block as given here, but giving 1 to 8 channels have a timing issue, while generating the build. So I thought it as an alternative plan. https://gitlab.com/theseus-cores/theseus-cores/-/blob/master/fpga-rfnoc/README.md#dsp-utilsnoc_block_ddc_1_to_n What was the timing issue? Is it possible for you to break up the logic to help relax timing constraints? Brian _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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