[USRP-users] timeouts problems with custom DUC multi channel

[Carlos Alberto Ruiz Naranjo via USRP-users]

Hi,

I have modified the DUC block to do it 2inputs-1outputs. The output is
duc_0 + duc_1.

input_0  ---> duc_0 --->
                                        cadd ---> output
input_1  ---> duc_1 --->

Apparently it works fine, but after 1 second I have timeout problems and
the output is weird.

cadd is the Ettus complex adder (
https://github.com/EttusResearch/fpga/blob/UHD-3.15.LTS/usrp3/lib/rfnoc/cadd.v)
3.15LTS

I think that it due the tvalid/tready. If I use (
https://github.com/EttusResearch/fpga/blob/UHD-3.15.LTS/usrp3/lib/rfnoc/cadd.v#L23
):

   assign int_tvalid = a_tvalid & b_tvalid;
*   assign a_tready = int_tvalid & int_tready;*
   assign b_tready = a_tready;

a_tready and b_tready are always '0' and I haven't any output. But if I use:

   assign int_tvalid = a_tvalid & b_tvalid;
*   assign a_tready = int_tready; //Independent tready*
   assign b_tready = a_tready;

I have the timeout problems. Why is tready dependent of tvalid?

Thank you.

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