Thank you Rob :) I have fixed the problem with the adder between axi_rate_change dds_timed.
El jue., 4 jun. 2020 a las 0:13, Rob Kossler (<rkoss...@nd.edu>) escribió: > I think that it is dependent on tvalid because both "a" and "b" need to be > consumed on the same sample. So, the code does not assert tready for > either input until the tvalid is asserted for both inputs. > > On Wed, Jun 3, 2020 at 6:06 AM Carlos Alberto Ruiz Naranjo via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> >> I have modified the DUC block to do it 2inputs-1outputs. The output is >> duc_0 + duc_1. >> >> input_0 ---> duc_0 ---> >> cadd ---> output >> input_1 ---> duc_1 ---> >> >> Apparently it works fine, but after 1 second I have timeout problems and >> the output is weird. >> >> cadd is the Ettus complex adder ( >> https://github.com/EttusResearch/fpga/blob/UHD-3.15.LTS/usrp3/lib/rfnoc/cadd.v) >> 3.15LTS >> >> I think that it due the tvalid/tready. If I use ( >> https://github.com/EttusResearch/fpga/blob/UHD-3.15.LTS/usrp3/lib/rfnoc/cadd.v#L23 >> ): >> >> assign int_tvalid = a_tvalid & b_tvalid; >> * assign a_tready = int_tvalid & int_tready;* >> assign b_tready = a_tready; >> >> a_tready and b_tready are always '0' and I haven't any output. But if I >> use: >> >> assign int_tvalid = a_tvalid & b_tvalid; >> * assign a_tready = int_tready; //Independent tready* >> assign b_tready = a_tready; >> >> I have the timeout problems. Why is tready dependent of tvalid? >> >> Thank you. >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >
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