If I want to use slot A as transmitter, slot B as receiver, can I do like
this:
self.source.set_antenna("RX2", 1)
self.sink.set_antenna("TX/RX", 0)In this page, it said *The default subdev spec is "A:0 B:0", which means slot A is mapped to channel 0, and slot B is mapped to channel 1.* http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2018-June/056965.html On Thu, Feb 18, 2021 at 9:18 PM Marcus D. Leech <[email protected]> wrote: > On 02/18/2021 10:16 PM, Xiang Ma wrote: > > Are there any python code for this? I am using the python interface. > > You'll have to kind of infer what to do from the C++ example--there is no > Python version of that example. > > > > On Thu, Feb 18, 2021 at 7:44 PM Marcus D Leech <[email protected]> > wrote: > >> Well there’s the rx_multi_samples example that is part of the UHD source >> tree. >> >> Sent from my iPhone >> >> On Feb 18, 2021, at 9:32 PM, Xiang Ma <[email protected]> wrote: >> >> >> Do you have any example code? I am still confused. >> >> Thank you. >> >> On Thu, Feb 18, 2021 at 5:50 PM Marcus D Leech <[email protected]> >> wrote: >> >>> Just create a 2-channel USRP source and specify a subdev of “A:0 B:0”. >>> >>> >>> >>> Sent from my iPhone >>> >>> On Feb 18, 2021, at 7:38 PM, Xiang Ma via USRP-users < >>> [email protected]> wrote: >>> >>> >>> Hi, >>> >>> I am using a x310 USRP with two UBX daughterboards. Now I can >>> transmit and receive the signal in RF A daughterboard with command >>> self.source.set_antenna("RX2", 0) >>> self.sink.set_antenna("TX/RX", 0). >>> >>> Now, I want to transmit the signal in RF A, and receive the signal >>> in both RF A and RF B. It is actually 1 transmitter and 2 receivers. How >>> can I implement this? I checked the set_subdev_subdev("B", 1), but it >>> doesn't work. >>> >>> Thank you, >>> >>> >>> >>> >>> -- >>> *Xiang Ma, *Ph.D. Student >>> College of Engineering >>> Utah State University >>> E-mail:[email protected] >>> _______________________________________________ >>> USRP-users mailing list >>> [email protected] >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >> >> -- >> *Xiang Ma, *Ph.D. Student >> College of Engineering >> Utah State University >> E-mail:[email protected] >> >> > > -- > *Xiang Ma, *Ph.D. Student > College of Engineering > Utah State University > E-mail:[email protected] > > > -- *Xiang Ma, *Ph.D. Student College of Engineering Utah State University E-mail:[email protected]
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