Okay, I think I answered my own question. Also, thanks to the work that
Cédric and Wade did to resolve a simulation issue during GUI mode back
in January.
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2021-January/063502.html
First, as Cédric and Wade resolved, modify the end of the testbench to
replace:
test.end_tb(); with
test.end_tb(0);
$finish();
Then, in RFNoC build directory run "make rfnoc_block_<your_block>_tb GUI=1
This opens up Vivado so you can run interactively (i.e. select which
signals you want to monitor).
Also, omitting GUI=1 will run in CLI mode and still output the testbench
results correctly.
As a secondary path for viewing simulation results I was able to execute
the following to view the results of a previous simulation.
# go to the location in your rfnoc folder where the simulation occured
cd
~/gr_dev/gr38/rfnoc/rfnoc-tutorial/rfnoc/fpga/rfnoc_block_gain/xsim_proj/xsim_proj.sim/sim_1/behav/xsim
# source the vivado environment variables
source ~/prefix/gr38/src/uhd/fpga/usrp3/top/e31x/setupenv.sh
# run xsim with the snapshot that was created during the original "make
rfnoc_block_xxx_tb"
xsim rfnoc_block_gain_tb_behav -gui -wdb rfnoc_block_gain_tb_behav.wdb
-view rfnoc_block_gain_tb_behav.wcfg
Thanks all for posting your problems and solutions. Sometimes it takes
a while to locate the correct answer but there is a lot of good
information on this list.
Mike
On 2/27/21 6:21 PM, Mike via USRP-users wrote:
Hi,
I'd like to view the signals in my testbench with a waveform viewer to
see things like latency of control signals vs. data through various
components. For instance, if I use a hardware multiplier (DSP48) with
registers I need to also delay the control signals to match the delay
in the processing. For simple things I can predict the latency and
use the top level test results to see if things calculated correctly.
But, it quickly gets to the point where you need to see what your
signals are doing.
I see that the simulation results produces a *.wdb file and maybe I
can use that to review the results of the simulation. But I didn't
know if there was another way to generate the waveforms and run the
simulation in GUI mode where you can add signals, restart, etc.
There is a warning that is printed in the simulation run that states:
WARNING: Simulation object /rfnoc_block_gain_tb/blk_ctrl was not
traceable in the design for the following reason:
Vivado Simulator does not support tracing of System Verilog Dynamic
Type object.
Anyway, any help is much appreciated.
Mike
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