Hi Rob, Thanks for your reply.
On 06/04/21 18:53, Rob Kossler wrote: > On Tue, Apr 6, 2021 at 12:41 PM Cédric Hannotier via USRP-users < > [email protected]> wrote: > > I would like to build a FPGA image with a replay block for E312. > > However, there is no dram_clk on this device. > > How should I instantiate my replay in my .yml? > > Perhaps Ettus can answer definitively, but in past emails I have had with > Wade Fife, he has indicated that there is currently no support for the > Replay block on the E310 (& thus I assume E312) and that the DRAM itself is > not presently supported from RFNoC. From the "USRP™ E312 Certificate of Volatility", there is a "DDR3L SDRAM - Micron" with 512 MB of memory dedicated for the "FPGA & User application memory". Furthermore, there are some commented lines with "ddr3" and "pl_dram" in "fpga/usrp3/top/e31x/e31x.v". My uneducated guess tells me it should be possible to use the replay block, somehow. The issue is while the E312 can go as far as 56 MHz of bandwidth, the ARM can only follow up to 10 MSps. I am trying to reach 20 MSps. Could we get an answer from Ettus regarding this issue? Kind regards -- Cédric Hannotier _______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
