Dear all,
I would like to build a FPGA image with a replay block for E312.
However, there is no dram_clk on this device.
How should I instantiate my replay in my .yml?
My modification so far:
diff --git a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml
b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml
index aa464454e..3e649caa1 100644
--- a/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml
+++ b/fpga/usrp3/top/e31x/e310_rfnoc_image_core.yml
@@ -20,12 +20,21 @@ stream_endpoints:
ctrl: False # Endpoint passes control traffic
data: True # Endpoint passes data traffic
buff_size: 16384 # Ingress buffer size for data
+ ep4: # Stream endpoint name
+ ctrl: False # Endpoint passes control traffic
+ data: True # Endpoint passes data traffic
+ buff_size: 4096 # Ingress buffer size for data
# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:
radio0: # NoC block name
block_desc: 'radio_2x64.yml' # Block device descriptor
+ replay0:
+ block_desc: 'replay.yml'
+ parameters:
+ NUM_PORTS: 1
+ MEM_ADDR_W: 30
# A list of all static connections in design
# ------------------------------------------
@@ -42,6 +51,10 @@ connections:
- { srcblk: radio0, srcport: ctrl_port, dstblk: _device_, dstport:
ctrlport_radio }
- { srcblk: _device_, srcport: x300_radio, dstblk: radio0, dstport:
x300_radio }
- { srcblk: _device_, srcport: time_keeper, dstblk: radio0, dstport:
time_keeper }
+ # ep4 & replay0
+ - { srcblk: ep4, srcport: out0, dstblk: replay0, dstport: in_0 }
+ - { srcblk: replay0, srcport: out_0, dstblk: ep4, dstport: in0 }
+ - { srcblk: replay0, srcport: axi_ram, dstblk: _device_, dstport: dram }
# A list of all clock domain connections in design
# ------------------------------------------------
@@ -52,3 +65,4 @@ connections:
# - dstport = Clock domain on the destination block to connect
clk_domains:
- { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
+ - { srcblk: _device_, srcport: dram, dstblk: replay0, dstport: mem }
--
Cédric Hannotier
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