Hi all, I have broken the code for my RFNoC block into a couple of different Verilog modules to help with single file complexity. Unfortunately, when I try to build the image it doesn’t find the module files when I put them in fpga/ directory of the OOT tree module. I have also tried one of the UHD lib directories where other .v modules are located but that doesn’t seem to work either.
Where should these files go? Thank you, Rylee Mattingly University of Oklahoma Graduate Research Assistant Email: [email protected]<mailto:[email protected]>
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