Hi Rylee, did you add the files to the Makefile or Makefile.inc or Makefile.srcs (depending on where your files ended up in) that contains the instruction to build your main module .v file?
Best regards, Marcus DISCLAIMER: Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system, or for use in hazardous environments. You assume all risks for use of the Code. Use of the Code is subject to terms of the licenses to the UHD or RFNoC code with which the Code is used. Standard licenses to UHD and RFNoC can be found at https://www.ettus.com/sdr-software/licenses/. NI will only perform services based on its understanding and condition that the goods or services (i) are not for the use in the production or development of any item produced, purchased, or ordered by any entity with a footnote 1 designation in the license requirement column of Supplement No. 4 to Part 744, U.S. Export Administration Regulations and (ii) such a company is not a party to the transaction. If our understanding is incorrect, please notify us immediately because a specific authorization may be required from the U.S. Commerce Department before the transaction may proceed further. On 10.04.21 23:15, Mattingly, Rylee wrote: > > > > I have broken the code for my RFNoC block into a couple of different Verilog > modules to > help with single file complexity. Unfortunately, when I try to build the > image it > doesn’t find the module files when I put them in fpga/ directory of the OOT > tree module. > I have also tried one of the UHD lib directories where other .v modules are > located but > that doesn’t seem to work either. > > > _______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
