If you write your own RFNoC block using axi_rate_change, you can go as large as you want. I don't know what the FPGA can "fit". The Xilinx FFT IP core allows you to trade-off throughput for resources. So, if you don't need full throughput, you can choose either radix-2 or radix-4 which will reduce resource usage.
Rob On Tue, May 4, 2021 at 5:11 PM <[email protected]> wrote: > > In this case, what would be the max fft length we can use? the Xilinx FFT can > handle up to 2**16 and the localparam in the rfnoc fft block is 2**11. > > Thank you. > > _______________________________________________ > USRP-users mailing list -- [email protected] > To unsubscribe send an email to [email protected] _______________________________________________ USRP-users mailing list -- [email protected] To unsubscribe send an email to [email protected]
