Rob, I think that requires (or used to require) a patch. The fixes to the 
DDC/DUC may have been merged, but i think the patch also added an option to the 
RFNoC ‘graph’ block to set skip propagation = True. That may have been related 
to the bugs in DDC/DUC. Unsure as it’s been a few months since I worked with 
it. 

<end transmission>

> On Dec 20, 2021, at 11:53, Rob Kossler <[email protected]> wrote:
> 
> 
> Not sure if this will be helpful, but there is an example UHD program called 
> rfnoc_radio_loopback which I think does a similar function.
> Rob
> 
>> On Mon, Dec 20, 2021 at 10:00 AM Paul Atreides <[email protected]> 
>> wrote:
>> For what it’s worth, the RFNoC blocks are included in GNURadio 3.9 in both 
>> maint-3.9 and tag 3.9.4
>> I haven’t tested them yet, but it appears as though they are actively being 
>> maintained. 
>> 
>> <end transmission>
>> 
>> > On Dec 20, 2021, at 05:26, Michael Hermann <[email protected]> 
>> > wrote:
>> > 
>> > Hello,
>> > 
>> > i am currently working on a small project using an USRP X310 combined with 
>> > UHD 4.0, gr-ettus 3.8 and GNUradio 3.8 on Ubuntu 20.04.
>> > The final goal would be to implement the following flowgraph on an FPGA 
>> > without transferring data to the host in between:
>> > 
>> > RX Radio ( -> DDC) -> FIR (-> DUC) -> TX Radio
>> > 
>> > I followed the workshop example and implemented the gain block 
>> > successfully and it works for the mentioned examples. I tried to implement 
>> > the above mentioned flowgraph with the gain block instead of a FIR filter 
>> > for testing purposes. This setup does not seem to work correctly even 
>> > tough GNUradio does not display any errors messages. The TX Radio does not 
>> > transmit a signal, even if there is an input on the RX Radio Part. Weirdly 
>> > enough, if i use the following flowgraph
>> > 
>> > RX Radio  -> DDC -> RX Streamer -> TX Streamer -> gain -> DUC -> TX Radio
>> > 
>> > the setup works and successfully relays the signal but routes the data 
>> > through the host which i want to avoid since the goal is to fully process 
>> > the signal on the FPGA.
>> > 
>> > Greetings and thanks in advance,
>> > Michael
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